X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/pwm.git/blobdiff_plain/a4ddd4bf8e12f8c15bb6766afc87601a72bcd2e0..e5b5df3bc6a94b429ac063ae078d1b5c4066d2ca:/tb/tb_mcc.vhd

diff --git a/tb/tb_mcc.vhd b/tb/tb_mcc.vhd
index d08d85f..c74ee61 100644
--- a/tb/tb_mcc.vhd
+++ b/tb/tb_mcc.vhd
@@ -16,7 +16,6 @@ architecture testbench of tb_mcc is
   constant LUT_DAT_W     : integer := 10;
   constant LUT_ADR_W     : integer := 9;
   constant LUT_INIT_FILE : string  := "../sin.lut";
-  constant IRF_ADR_W     : integer := 5;
 
   constant WAVE_SIZE : integer := 2**LUT_ADR_W;
   
@@ -27,7 +26,7 @@ architecture testbench of tb_mcc is
   signal STB_I : std_logic;
 
   signal IRF_ACK_I : std_logic;
-  signal IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
+  signal IRF_ADR_O : std_logic_vector (4 downto 0);
   signal IRF_CYC_O : std_logic;
   signal IRF_DAT_I : std_logic_vector (15 downto 0);
   signal IRF_DAT_O : std_logic_vector (15 downto 0);
@@ -60,8 +59,7 @@ begin
   uut : entity work.mcc
     generic map (
       LUT_ADR_W => LUT_ADR_W,
-      LUT_DAT_W => LUT_DAT_W,
-      IRF_ADR_W => IRF_ADR_W)
+      LUT_DAT_W => LUT_DAT_W)
     port map (
       ACK_O      => ACK_O,
       CLK_I      => CLK_I,