library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_mcc is
end tb_mcc;

--------------------------------------------------------------------------------

architecture testbench of tb_mcc is

  constant period : time := 500 ns;
  constant offset : time := 0 us;

  constant LUT_DAT_W     : integer := 10;
  constant LUT_ADR_W     : integer := 9;
  constant LUT_INIT_FILE : string  := "../sin.lut";
  constant IRF_ADR_W     : integer := 5;

  constant WAVE_SIZE : integer := 2**LUT_ADR_W;
  

  signal ACK_O : std_logic;
  signal CLK_I : std_logic;
  signal RST_I : std_logic;
  signal STB_I : std_logic;

  signal IRF_ACK_I : std_logic;
  signal IRF_ADR_O : std_logic_vector (IRF_ADR_W-1 downto 0);
  signal IRF_CYC_O : std_logic;
  signal IRF_DAT_I : std_logic_vector (15 downto 0);
  signal IRF_DAT_O : std_logic_vector (15 downto 0);
  signal IRF_STB_O : std_logic;
  signal IRF_WE_O  : std_logic;

  signal LUT_ADR_O : std_logic_vector (LUT_ADR_W-1 downto 0);
  signal LUT_DAT_I : std_logic_vector (LUT_DAT_W-1 downto 0);
  signal LUT_STB_O : std_logic;

  
  subtype word_t is std_logic_vector (15 downto 0);
  
  signal dbg_mem00 : word_t    := "0000000000100100";  -- MCC enable flags (RO)
  signal dbg_mem04 : word_t    := (others => '0');     -- Angle            (RO)
  signal dbg_mem11 : word_t    := (others => '0');     -- Phase 1
  signal dbg_mem15 : word_t    := (others => '0');     -- Phase 2
  signal dbg_mem19 : word_t    := (others => '0');     -- Phase 3
  signal dbg_ack   : std_logic := '0';

--------------------------------------------------------------------------------

begin

  uut : entity work.mcc
    generic map (
      LUT_ADR_W => LUT_ADR_W,
      LUT_DAT_W => LUT_DAT_W,
      IRF_ADR_W => IRF_ADR_W)
    port map (
      ACK_O      => ACK_O,
      CLK_I      => CLK_I,
      RST_I      => RST_I,
      STB_I      => STB_I,
      LUT_STB_O  => LUT_STB_O,
      LUT_ADR_O  => LUT_ADR_O,
      LUT_DAT_I  => LUT_DAT_I,
      IRC_DAT_I  => (others => '0'),
      PWM_DAT_O  => open,
      PWM1_STB_O => open,
      PWM2_STB_O => open,
      PWM3_STB_O => open,
      IRF_ACK_I  => IRF_ACK_I,
      IRF_ADR_O  => IRF_ADR_O,
      IRF_DAT_I  => IRF_DAT_I,
      IRF_DAT_O  => IRF_DAT_O,
      IRF_STB_O  => IRF_STB_O,
      IRF_WE_O   => IRF_WE_O);

  wave_table_1 : entity work.wave_table
    generic map (
      DAT_W     => LUT_DAT_W,
      ADR_W     => LUT_ADR_W,
      INIT_FILE => LUT_INIT_FILE)
    port map (
      ACK_O => open,
      ADR_I => LUT_ADR_O,
      CLK_I => CLK_I,
      DAT_I => (others => '0'),
      DAT_O => LUT_DAT_I,
      STB_I => LUT_STB_O,
      WE_I  => '0');
  
  
  SYSCON_CLK : process is
  begin
    CLK_I <= '0';
    wait for offset;
    loop
      CLK_I <= '1';
      wait for period/2;
      CLK_I <= '0';
      wait for period/2;
    end loop;
  end process;

  SYSCON_RST : process is
  begin
    RST_I <= '0';
    wait for offset;
    wait for 0.75*period;
    RST_I <= '1';
    wait for 2*period;
    RST_I <= '0';
    wait;
  end process;

  
  DBG_MEM : process (IRF_STB_O, CLK_I) is
  begin
    IRF_ACK_I <= IRF_STB_O and (IRF_WE_O or dbg_ack);

    if rising_edge(CLK_I) then
      dbg_ack <= IRF_STB_O;
    end if;

    if rising_edge(CLK_I) and IRF_STB_O = '1' then
      if IRF_WE_O = '0' then
        case conv_integer(IRF_ADR_O) is
          when 16#00# => IRF_DAT_I <= dbg_mem00;
          when 16#04# => IRF_DAT_I <= dbg_mem04;
          when 16#11# => IRF_DAT_I <= dbg_mem11;
          when 16#15# => IRF_DAT_I <= dbg_mem15;
          when 16#19# => IRF_DAT_I <= dbg_mem19;
          when others => IRF_DAT_I <= (others => '0');
        end case;
      else
        case conv_integer(IRF_ADR_O) is
          when 16#11# => dbg_mem11 <= IRF_DAT_O;
          when 16#15# => dbg_mem15 <= IRF_DAT_O;
          when 16#19# => dbg_mem19 <= IRF_DAT_O;
          when others => null;
        end case;
      end if;
    end if;
  end process;
  
--------------------------------------------------------------------------------

  UUT_FEED : process is
  begin
    STB_I <= '0';
        
    wait for offset;
    wait for 4*period;

    for i in 0 to 1 loop
      dbg_mem04 <= conv_std_logic_vector(i, 16);
      
      STB_I <= '1';
      wait until rising_edge(CLK_I) and ACK_O = '1';
      STB_I <= '0';
      wait for 4*period;
    end loop;
    
    wait;
  end process;
  
end testbench;