library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

--------------------------------------------------------------------------------

entity pwm_min_dump is
  generic (
    IRF_ADR_W  : integer := 5;
    BASE       : integer := 0;
    PWMMIN_OFF : integer := 6;
    P_BASE     : integer := 16;
    PWM_OFF    : integer := 1;
    PWM_W      : integer := 10);
  port (
    -- Primary slave intefrace
    ACK_O     : out std_logic;
    CLK_I     : in  std_logic;
    RST_I     : in  std_logic;
    STB_I     : in  std_logic;
    -- PWM interface
    PWM_DAT_O : out std_logic_vector (PWM_W-1 downto 0);
    PWM_STB_O : out std_logic := '0';
    -- Shared dual-port memory
    IRF_ACK_I : in  std_logic;
    IRF_ADR_O : out std_logic_vector (IRF_ADR_W-1 downto 0);
    IRF_DAT_I : in  std_logic_vector (15 downto 0);
    IRF_STB_O : out std_logic);
end entity pwm_min_dump;

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architecture behavioral of pwm_min_dump is

  type state_t is (ready, dump, done);
  subtype irf_adr_t is std_logic_vector (IRF_ADR_W-1 downto 0);

  constant PWMMIN_ADR : irf_adr_t := conv_std_logic_vector(BASE+PWMMIN_OFF, IRF_ADR_W);
  constant PWM_ADR    : irf_adr_t := conv_std_logic_vector(P_BASE + PWM_OFF, IRF_ADR_W);
  
  signal state : state_t := ready;

  signal ack     : std_logic := '0';
  --signal pwm_min : std_logic_vector (PWM_DAT_O'RANGE);
  signal pwm_min : std_logic_vector (PWM_DAT_O'range);
  signal pwm_stb : std_logic := '0';
  signal irf_adr : irf_adr_t := PWMMIN_ADR;
  signal irf_we  : std_logic := '0';
  
--------------------------------------------------------------------------------

begin

  ACK_O <= STB_I and ack;

  PWM_DAT_O <= IRF_DAT_I(pwm_min'RANGE) - pwm_min;
  PWM_STB_O <= pwm_stb;
  
  IRF_ADR_O <= irf_adr;
  IRF_STB_O <= STB_I;

  
  FSM : process (CLK_I, RST_I) is
  begin
    if RST_I = '1' then
      state   <= ready;
      ack     <= '0';
      irf_adr <= PWMMIN_ADR;
      pwm_stb <= '0';
      
    elsif rising_edge(CLK_I) then
      case state is
        when ready =>
          if STB_I = '1' then
            state   <= dump;
            irf_adr <= PWM_ADR;
          end if;
          
        when dump =>
          state   <= done;
          ack     <= '1';
          pwm_stb <= '1';
          pwm_min <= IRF_DAT_I(pwm_min'RANGE);

        when done =>
          pwm_stb <= '0';
          if STB_I = '0' then
            state   <= ready;
            ack     <= '0';
            irf_adr <= PWMMIN_ADR;
          end if;
      end case;
    end if;
  end process;
  
end architecture behavioral;