library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

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entity pwm3 is
  generic (
    PWM_W : integer);
  port (
    CLK     : in  std_logic;
    RST     : in  std_logic;
    DAT     : in  std_logic_vector (PWM_W-1 downto 0);
    SEL     : in  std_logic
    WE      : in  std_logic (2 downto 0);
    -- PWM interface
    PWM_CNT : in  std_logic_vector (PWM_W-1 downto 0)
    PWM_CYC : in  std_logic;
    PWM     : out std_logic_vector (2 downto 0));
end pwm3;

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architecture rtl of pwm3 is
begin

  PWM_GEN : for i in 0 to 2 generate
    pwm_1 : entity work.pwm
      generic map (
        PWM_WIDTH => PWM_W)
      port map (
        clk     => CLK,
        reset   => RST,
        din     => DAT,
        sel     => SEL,
        we      => WE (i),
        pwm_cnt => PWM_CNT,
        pwm_cyc => PWM_CYC,
        pwm     => PWM (i));
  end generate PWM_GEN;

end rtl;