library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------------------------------- entity mcc_exec is generic ( AXIS_CNT : integer := 1; AXIS_CNT_W : integer := 1); port ( -- Clock & reset CLK_I : in std_logic; RST_I : in std_logic; -- MCC execution MCC_AXIS_O : out std_logic_vector (AXIS_CNT_W-1 downto 0); MCC_DONE_O : out std_logic; MCC_EN_I : in std_logic; MCC_EXEC_I : in std_logic; MCC_ERR_O : out std_logic; -- MCC master interface MCC_ACK_I : in std_logic; MCC_STB_O : out std_logic); end entity mcc_exec; -------------------------------------------------------------------------------- architecture behavioral of mcc_exec is type state_t is (ready, do); signal state : state_t := ready; signal mcc_axis : std_logic_vector (MCC_AXIS_O'range); signal mcc_done : std_logic := '0'; signal mcc_stb : std_logic := '0'; -------------------------------------------------------------------------------- begin assert (AXIS_CNT <= 2**AXIS_CNT_W) report "Insufficient count of bits in MCC_AXIS_O to express axis number." severity error; MCC_AXIS_O <= mcc_axis; MCC_DONE_O <= mcc_done; MCC_ERR_O <= '1' when (MCC_EXEC_I = '1' and state = do) else '0'; MCC_STB_O <= mcc_stb; FSM : process (CLK_I) is begin if rising_edge(CLK_I) then if RST_I = '1' then state <= ready; mcc_done <= '0'; mcc_stb <= '0'; else case state is when ready => mcc_stb <= '0'; mcc_done <= '0'; if MCC_EXEC_I = '1' and MCC_EN_I = '1' then state <= do; mcc_stb <= '1'; mcc_axis <= conv_std_logic_vector(0,AXIS_CNT_W); end if; when do => mcc_stb <= '1'; if MCC_ACK_I = '1' then mcc_stb <= '0'; if mcc_axis = (AXIS_CNT-1) then state <= ready; mcc_done <= '1'; else mcc_axis <= mcc_axis + 1; end if; end if; end case; end if; end if; end process; end architecture behavioral;