library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tb_pwm is
end tb_pwm;

--------------------------------------------------------------------------------

architecture testbench of tb_pwm is

  constant period : time := 250 ns;
  constant offset : time := 0 us;


  constant PWM_W   : integer := 2;
  constant CNT_MAX : integer := 2**PWM_W - 2;

  
  signal clk      : std_logic;
  signal reset    : std_logic;
  signal din      : std_logic_vector (PWM_W-1 downto 0);
  signal we       : std_logic;
  signal pwm_cnt  : std_logic_vector (PWM_W-1 downto 0);
  signal pwm_cyc  : std_logic;
  signal pwm_out  : std_logic;

--------------------------------------------------------------------------------

  component pwm is
    generic (
      PWM_WIDTH : integer);
    port (
      clk     : in  std_logic;
      reset   : in  std_logic;
      din     : in  std_logic_vector (PWM_WIDTH-1 downto 0);
      we      : in  std_logic;
      pwm_cnt : in  std_logic_vector (PWM_WIDTH-1 downto 0);
      pwm_cyc : in  std_logic;
      pwm     : out std_logic);
  end component pwm;

  component counter is
    generic (
      WIDTH : integer;
      MAX   : integer);
    port (
      clk      : in  std_logic;
      reset    : in  std_logic;
      count    : out std_logic_vector (WIDTH-1 downto 0);
      event_ow : out std_logic);
  end component counter;
  
--------------------------------------------------------------------------------
  
begin

  uut : pwm
    generic map (
      PWM_WIDTH => PWM_W)
    port map (
      clk     => clk,
      reset   => reset,
      din     => din,
      we      => we,
      pwm_cnt => pwm_cnt,
      pwm_cyc => pwm_cyc,
      pwm     => pwm_out);
  
  counter_1 : counter
    generic map (
      WIDTH => PWM_W,
      MAX   => CNT_MAX)
    port map (
      clk      => clk,
      reset    => reset,
      count    => pwm_cnt,
      event_ow => pwm_cyc);

  
  CLK_PROC : process
  begin
    clk <= '0';
    wait for offset;
    
    loop
      clk <= '1';
      wait for period/2;
      clk <= '0';
      wait for period/2;
    end loop;
  end process;


  RSET_PROC : process
  begin
    reset <= '0';
    wait for 1.5 * period;
    reset <= '1';
    wait for 1 * period;
    reset <= '0';
    wait;
  end process;


  ADDR_PROC : process
  begin
    din <= (others => '0');
    we  <= '0';
    
    wait for offset;
    wait for 3 * period;
    
    for i in 0 to 2*(2**PWM_W)-1 loop
      din <= conv_std_logic_vector(i, PWM_W);
      we <= '1';
      wait for period;
      we <= '0';
      wait for 12*period;
    end loop;
    
    wait;
  end process;
  
end testbench;