From: Vladimir Burian Date: Thu, 10 Mar 2011 12:13:19 +0000 (+0100) Subject: Added samples of Coregen memories. X-Git-Url: http://rtime.felk.cvut.cz/gitweb/fpga/openmsp430.git/commitdiff_plain/7a8cb70f0fb2f4a71cfe1780e4221cc4484650bb Added samples of Coregen memories. Compiled files, vhdl wrappers and templates of *.bmm files are included. --- diff --git a/memory/coregen/coregen.cgp b/memory/coregen/coregen.cgp new file mode 100644 index 0000000..a3101b6 --- /dev/null +++ b/memory/coregen/coregen.cgp @@ -0,0 +1,19 @@ +# Date: Sat Jan 8 21:37:24 2011 +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True + diff --git a/memory/coregen/ram_8x2k.ngc b/memory/coregen/ram_8x2k.ngc new file mode 100644 index 0000000..e7e82e1 --- /dev/null +++ b/memory/coregen/ram_8x2k.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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=> "1024", + c_yhierarchy => "hierarchy1", + c_has_limit_data_pitch => 0, + c_has_rdy => 0, + c_write_mode => 0, + c_width => 8, + c_yuse_single_primitive => 0, + c_has_nd => 0, + c_has_we => 1, + c_enable_rlocs => 0, + c_has_rfd => 0, + c_has_din => 1, + c_ybottom_addr => "0", + c_pipe_stages => 0, + c_yen_is_high => 0, + c_depth => 2048, + c_has_default_data => 1, + c_limit_data_pitch => 18, + c_has_sinit => 0, + c_yydisable_warnings => 1, + c_mem_init_file => "mif_file_16_1", + c_default_data => "0", + c_ymake_bmm => 0, + c_addr_width => 11); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram_8x2k + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- synthesis translate_on + +END ram_8x2k_a; + diff --git a/memory/coregen/ram_8x2k.xco b/memory/coregen/ram_8x2k.xco new file mode 100644 index 0000000..d9bcfa0 --- /dev/null +++ b/memory/coregen/ram_8x2k.xco @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version J.36 +# Date: Sun Mar 6 15:37:58 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET active_clock_edge=Rising_Edge_Triggered +CSET additional_output_pipe_stages=0 +CSET component_name=ram_8x2k +CSET depth=2048 +CSET disable_warning_messages=true +CSET enable_pin=true +CSET enable_pin_polarity=Active_Low +CSET global_init_value=0 +CSET handshaking_pins=false +CSET has_limit_data_pitch=false +CSET init_pin=false +CSET init_value=0 +CSET initialization_pin_polarity=Active_High +CSET limit_data_pitch=18 +CSET load_init_file=false +CSET port_configuration=Read_And_Write +CSET primitive_selection=Optimize_For_Area +CSET register_inputs=false +CSET select_primitive=16kx1 +CSET width=8 +CSET write_enable_polarity=Active_Low +CSET write_mode=Read_After_Write +# END Parameters +GENERATE +# CRC: 194ee8e4 + diff --git a/memory/coregen/ram_8x4k.ngc b/memory/coregen/ram_8x4k.ngc new file mode 100644 index 0000000..de8c4f3 --- /dev/null +++ b/memory/coregen/ram_8x4k.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file ram_8x4k.vhd when simulating +-- the core, ram_8x4k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY ram_8x4k IS + port ( + addr: IN std_logic_VECTOR(11 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +END ram_8x4k; + +ARCHITECTURE ram_8x4k_a OF ram_8x4k IS +-- synthesis translate_off +component wrapped_ram_8x4k + port ( + addr: IN std_logic_VECTOR(11 downto 0); + clk: IN std_logic; + din: IN std_logic_VECTOR(7 downto 0); + dout: OUT std_logic_VECTOR(7 downto 0); + en: IN std_logic; + we: IN std_logic); +end component; + +-- Configuration specification + for all : wrapped_ram_8x4k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral) + generic map( + c_sinit_value => "0", + c_has_en => 1, + c_reg_inputs => 0, + c_yclk_is_rising => 1, + c_ysinit_is_high => 1, + c_ywe_is_high => 0, + c_yprimitive_type => "16kx1", + c_ytop_addr => "1024", + c_yhierarchy => "hierarchy1", + c_has_limit_data_pitch => 0, + c_has_rdy => 0, + c_write_mode => 0, + c_width => 8, + c_yuse_single_primitive => 0, + c_has_nd => 0, + c_has_we => 1, + c_enable_rlocs => 0, + c_has_rfd => 0, + c_has_din => 1, + c_ybottom_addr => "0", + c_pipe_stages => 0, + c_yen_is_high => 0, + c_depth => 4096, + c_has_default_data => 1, + c_limit_data_pitch => 18, + c_has_sinit => 0, + c_yydisable_warnings => 1, + c_mem_init_file => "mif_file_16_1", + c_default_data => "0", + c_ymake_bmm => 0, + c_addr_width => 12); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ram_8x4k + port map ( + addr => addr, + clk => clk, + din => din, + dout => dout, + en => en, + we => we); +-- synthesis translate_on + +END ram_8x4k_a; + diff --git a/memory/coregen/ram_8x4k.xco b/memory/coregen/ram_8x4k.xco new file mode 100644 index 0000000..3dd8fa0 --- /dev/null +++ b/memory/coregen/ram_8x4k.xco @@ -0,0 +1,63 @@ +############################################################## +# +# Xilinx Core Generator version J.36 +# Date: Sun Mar 6 15:38:31 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc2v1000 +SET devicefamily = virtex2 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -6 +SET verilogsim = False +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET active_clock_edge=Rising_Edge_Triggered +CSET additional_output_pipe_stages=0 +CSET component_name=ram_8x4k +CSET depth=4096 +CSET disable_warning_messages=true +CSET enable_pin=true +CSET enable_pin_polarity=Active_Low +CSET global_init_value=0 +CSET handshaking_pins=false +CSET has_limit_data_pitch=false +CSET init_pin=false +CSET init_value=0 +CSET initialization_pin_polarity=Active_High +CSET limit_data_pitch=18 +CSET load_init_file=false +CSET port_configuration=Read_And_Write +CSET primitive_selection=Optimize_For_Area +CSET register_inputs=false +CSET select_primitive=16kx1 +CSET width=8 +CSET write_enable_polarity=Active_Low +CSET write_mode=Read_After_Write +# END Parameters +GENERATE +# CRC: d918621d + diff --git a/memory/coregen/template.bmm b/memory/coregen/template.bmm new file mode 100644 index 0000000..1c76510 --- /dev/null +++ b/memory/coregen/template.bmm @@ -0,0 +1,21 @@ +/* Templates for initialization of memories created by Xilinx Coregen using + data2mem tool. */ + +/* Overall size of 8kB (2x4Kb) */ +ADDRESS_SPACE blockrom RAMB16 [0xe000:0xffff] + BUS_BLOCK + rom_8x4k_lo/B12 [7:4]; + rom_8x4k_lo/B8 [3:0]; + rom_8x4k_hi/B12 [15:12]; + rom_8x4k_hi/B8 [11:8]; + END_BUS_BLOCK; +END_ADDRESS_SPACE; + +/* Overall size of 4kB (2x2kB) */ +ADDRESS_SPACE blockrom RAMB16 [0xf000:0xffff] + BUS_BLOCK + rom_8x2k_lo/B8 [7:0]; + rom_8x2k_hi/B8 [15:8]; + END_BUS_BLOCK; +END_ADDRESS_SPACE; +