Add back support for delay slot, but with writing PC+4 when linking and using delay...

[fpga/lx-cpu1/tumbl.git] / hw / mbl_Pkg.vhd

diff --git a/hw/mbl_Pkg.vhd b/hw/mbl_Pkg.vhd
index 0f48b09c203e4d1ce645c25aa0bb1c05dab19fe4..ec7c25bc3559d2afce3b52857f271f72fff54557 100644 (file)
--- a/hw/mbl_Pkg.vhd
+++ b/hw/mbl_Pkg.vhd
@@ -213,9 +213,7 @@ PACKAGE mbl_Pkg IS
                ID2EX_o     : OUT ID2EX_Type;
                --
                INT_CTRL_i  :  IN INT_CTRL_Type;
-               ID2CTRL_o   : OUT ID2CTRL_Type;
-               --
-               noLiteOpc_o : OUT STD_LOGIC
+               ID2CTRL_o   : OUT ID2CTRL_Type
        );
        END COMPONENT;
 
@@ -228,7 +226,10 @@ PACKAGE mbl_Pkg IS
        );
        PORT
        (
+               IF2ID_i      :  IN IF2ID_Type;
+               --
                ID2EX_i      :  IN ID2EX_Type;
+               delayBit_i   :  IN STD_LOGIC;
                GPRF2EX_i    :  IN GPRF2EX_Type;
                EX2IF_o      : OUT EX2IF_Type;
                EX2CTRL_o    : OUT EX2CTRL_Type;
@@ -277,7 +278,6 @@ PACKAGE mbl_Pkg IS
                clk_i           :  IN STD_LOGIC;
                rst_i           :  IN STD_LOGIC;
                halt_i          :  IN STD_LOGIC;
-               bad_op_i        :  IN STD_LOGIC;
                int_i           :  IN STD_LOGIC;
                trace_i         :  IN STD_LOGIC;
                trace_kick_i    :  IN STD_LOGIC;
@@ -292,6 +292,7 @@ PACKAGE mbl_Pkg IS
                -- decode to exeq pipeline registers
                ID2EX_REG_i     :  IN ID2EX_Type;
                ID2EX_REG_o     : OUT ID2EX_Type;
+               delay_bit_o     : OUT STD_LOGIC;
                -- GPRF control
                gprf_clken_o    : OUT STD_LOGIC;
                -- exeq to fetch feedback registers