ID2EX_o : OUT ID2EX_Type;
--
INT_CTRL_i : IN INT_CTRL_Type;
- ID2CTRL_o : OUT ID2CTRL_Type;
- --
- noLiteOpc_o : OUT STD_LOGIC
+ ID2CTRL_o : OUT ID2CTRL_Type
);
END ENTITY decode;
rB_v := instruction_v (15 DOWNTO 11);
IMM16_v := instruction_v (15 DOWNTO 0);
IMM_Lock_v := '0';
- IF (COMPATIBILITY_MODE_g = TRUE) THEN
- delayBit_v := '0';
- ELSE
+ delayBit_v := '0';
+ IF (COMPATIBILITY_MODE_g = FALSE) THEN
it_Action_v := NO_IT;
END IF;
condition_raw_v := (others => '1');
-- for decoding SEXT16, SEXT8, SRC, SRC or SRL
code_x26_v := instruction_v(6) & instruction_v(5) & instruction_v(0);
int_busy_v := INT_CTRL_i.int_busy;
- -- for debugging purposes
- noLiteOpc_o <= '0';
IF (INT_CTRL_i.setup_int = '1') THEN
WHEN "000" => -- MUL
IF (USE_HW_MUL_g = TRUE) THEN
alu_Action_v := A_MUL;
- ELSE
- noLiteOpc_o <= '1';
END IF;
WHEN "001" => -- BS
ELSE
alu_Action_v := A_BSRL;
END IF;
- ELSE
- noLiteOpc_o <= '1';
END IF;
WHEN "010" | "011" => -- CMP(U)
ELSE
alu_Action_v := A_CMP;
END IF;
- ELSE
- noLiteOpc_o <= '1';
END IF;
WHEN "100" | "101" => -- IT(U) / ITT(U) / ITE(U)
END IF;
CASE rD_v(4 downto 3) IS
- WHEN "00" =>
- it_Action_v := IT;
- WHEN "01" =>
- it_Action_v := ITT;
- WHEN "10" =>
- it_Action_v := ITE;
- WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ WHEN "00" => it_Action_v := IT;
+ WHEN "01" => it_Action_v := ITT;
+ WHEN "10" => it_Action_v := ITE;
+ WHEN OTHERS => NULL;
END CASE;
condition_raw_v := rD_v(2 downto 0);
-- IT instruction isn't writing to anything
wrb_Action_v := NO_WRB;
- ELSE
- noLiteOpc_o <= '1';
END IF;
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
WHEN "10" =>
WHEN "10" => -- SRL
alu_Cin_v := CIN_ZERO;
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
alu_Action_v := A_SHIFT;
msr_Action_v := UPDATE_CARRY;
WHEN "111" => -- SEXT16
alu_Action_v := A_SEXT16;
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
ELSIF (opcIx_v (3 DOWNTO 0) = "1100") THEN -- IMM
CASE rD_v (3 DOWNTO 0) IS
WHEN "0001" => -- RTI(D)
int_busy_v := '0';
- WHEN "0000" => -- RTS(D)
- WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ WHEN OTHERS => -- RTS(D)
+ NULL;
END CASE;
alu_Action_v := A_ADD;
branch_Action_v := BR;
wrb_Action_v := NO_WRB;
- IF (COMPATIBILITY_MODE_g = TRUE) THEN
- delayBit_v := rD_v(4);
- END IF;
+ delayBit_v := rD_v(4);
ELSIF (opcIx_v (3 DOWNTO 0) = "0101") THEN
alu_Action_v := A_MTS;
wrb_Action_v := NO_WRB;
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
rB_v := (OTHERS => '0'); -- in order to prevent occasional hazards (r16, r24)
END IF;
WHEN "110" => -- BR(I)(D)
- IF (rA_v(2) = '1') THEN
- branch_Action_v := BRL;
- ELSE
- branch_Action_v := BR;
- wrb_Action_v := NO_WRB;
- END IF;
-
IF (rA_v(3) = '1') THEN
alu_Op1_v := ALU_IN_ZERO;
ELSE
alu_Op1_v := ALU_IN_PC;
END IF;
- alu_Action_v := A_ADD;
- IF (COMPATIBILITY_MODE_g = TRUE) THEN
- delayBit_v := rA_v(4);
+
+ IF (rA_v(2) = '1') THEN
+ branch_Action_v := BRL;
+ ELSE
+ branch_Action_v := BR;
+ wrb_Action_v := NO_WRB;
END IF;
+ alu_Action_v := A_ADD;
+ delayBit_v := rA_v(4);
WHEN "111" =>
condition_raw_v := rD_v(2 downto 0); -- Conditional branching
branch_Action_v := BR;
- alu_Action_v := A_ADD;
- alu_Op1_v := ALU_IN_PC;
- IF (COMPATIBILITY_MODE_g = TRUE) THEN
- delayBit_v := rD_v(4);
- END IF;
- wrb_Action_v := NO_WRB; -- evaluate and update/overwrite in exeq
+ alu_Action_v := A_ADD;
+ alu_Op1_v := ALU_IN_PC;
+ delayBit_v := rD_v(4);
+ wrb_Action_v := NO_WRB; -- evaluate and update/overwrite in exeq
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
END IF;
WHEN "00" => transfer_Size_v := BYTE;
WHEN "01" => transfer_Size_v := HALFWORD;
WHEN "10" => transfer_Size_v := WORD;
- WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ WHEN OTHERS => NULL;
END CASE;
IF (opcIx_v(2) = '0') THEN
mem_Action_v := RD_MEM;
END IF;
WHEN OTHERS =>
- noLiteOpc_o <= '1';
+ NULL;
END CASE;
ID2EX_o.condition <= COND_ALL;
WHEN OTHERS =>
ID2EX_o.condition <= COND_ALL;
- noLiteOpc_o <= '1';
END CASE;
--
- IF (COMPATIBILITY_MODE_g = TRUE) THEN
- ID2CTRL_o.delayBit <= delayBit_v;
- END IF;
- ID2CTRL_o.int_busy <= int_busy_v;
+ ID2CTRL_o.delayBit <= delayBit_v;
+ ID2CTRL_o.int_busy <= int_busy_v;
END PROCESS;