From 258b9f32fef127226eb914eb85641961afb7be3a Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 22 Feb 2015 12:10:59 +0100 Subject: [PATCH] Testbed for receiver CRC processing check. Signed-off-by: Pavel Pisa --- hw/tb/Makefile | 2 +- hw/tb/firmware-for-rx-crc/Makefile | 94 ++++++++++++++++++++++++++ hw/tb/firmware-for-rx-crc/firmware.c | 70 +++++++++++++++++++ hw/tb/firmware-for-rx-crc/start.S | 29 ++++++++ hw/tb/firmware-for-rx-crc/tumbl_addr.h | 85 +++++++++++++++++++++++ hw/tb/firmware-for-rx-crc/utils | 1 + hw/tb/lx_rocon-rx-crc.gtkw | 51 ++++++++++++++ hw/tb/lx_rocon_top_tb.vhd | 16 +++++ 8 files changed, 347 insertions(+), 1 deletion(-) create mode 100644 hw/tb/firmware-for-rx-crc/Makefile create mode 100644 hw/tb/firmware-for-rx-crc/firmware.c create mode 100644 hw/tb/firmware-for-rx-crc/start.S create mode 100644 hw/tb/firmware-for-rx-crc/tumbl_addr.h create mode 120000 hw/tb/firmware-for-rx-crc/utils create mode 100644 hw/tb/lx_rocon-rx-crc.gtkw diff --git a/hw/tb/Makefile b/hw/tb/Makefile index c9fcb8f..6c789ec 100644 --- a/hw/tb/Makefile +++ b/hw/tb/Makefile @@ -42,7 +42,7 @@ test-tumbl: analyze-all imem.bits test-rocon: analyze-all imem.bits $(GHDL) $(GHDLFLAGS) -m $(ANALYZEFLAGS) lx_rocon_top_tb - $(GHDL) $(GHDLFLAGS) -r lx_rocon_top_tb --stop-time=10000ns --vcd=$@.vcd --wave=$@.ghw + $(GHDL) $(GHDLFLAGS) -r lx_rocon_top_tb --stop-time=100000ns --vcd=$@.vcd --wave=$@.ghw analyze-all: $(SRC) $(GHDL) $(GHDLFLAGS) -a $(ANALYZEFLAGS) $(SRC) diff --git a/hw/tb/firmware-for-rx-crc/Makefile b/hw/tb/firmware-for-rx-crc/Makefile new file mode 100644 index 0000000..ca45489 --- /dev/null +++ b/hw/tb/firmware-for-rx-crc/Makefile @@ -0,0 +1,94 @@ +#=============================================================================== +# Firmware + +OUT := _build +BUILDDIR := _build + +MB_CROSS_COMPILE ?= mbtumbl-elf- +TARGET_CC := $(MB_CROSS_COMPILE)gcc +TARGET_LD := $(MB_CROSS_COMPILE)ld +TARGET_OBJCOPY := $(MB_CROSS_COMPILE)objcopy +TARGET_OBJDUMP := $(MB_CROSS_COMPILE)objdump + +C_OBJS := $(OUT)/firmware.o +A_OBJS := +CFLAGS := -mxl-soft-div -msoft-float -Wno-main -Wl,-no-check-sections -fno-zero-initialized-in-bss +CFLAGS += -O2 -Wall +DEB_FLAGS += -g +AFLAGS := -D__ASSEMBLY__ $(CFLAGS) +LDFLAGS := -static -nostdlib -relax -defsym _STACK_SIZE=0x0200 + +OBJS := $(OUT)/start.o $(C_OBJS) $(A_OBJS) + +REQ_FIRMWARE := $(OUT)/imem.bin $(OUT)/imem.asm $(OUT)/dmem.bin $(OUT)/firmware.lst + +FIRMWARE_DIR := . + +USB_APP_VID_PID ?= 0x1669:0x1023 + +USB_SENDHEX := ./usb_sendhex + +#=============================================================================== + +# Attempt to create a output directory. +$(shell [ -d ${OUT} ] || mkdir -p ${OUT}) + +# Verify if it was successful. +OUTPUT_DIR := $(shell cd $(OUT) && /bin/pwd) +$(if $(OUTPUT_DIR),,$(error output directory "$(OUT)" does not exist)) + +#=============================================================================== + +.PHONY: all +all: firmware + +#$(OUT)/%.o: $(FIRMWARE_DIR)/%.c +# $(TARGET_CC) $(CFLAGS) $(DEB_FLAGS) -c $< -o $@ + +$(OUT)/%.s: $(FIRMWARE_DIR)/%.c + $(TARGET_CC) $(CFLAGS) $(DEB_FLAGS) -S $< -o $@ + +.PRECIOUS: $(OUT)/%.s + +$(OUT)/%.o: $(OUT)/%.s + $(TARGET_CC) $(AFLAGS) -fpreprocessed -c $< -o $@ + +$(OUT)/%.o: $(FIRMWARE_DIR)/%.S + $(TARGET_CC) $(AFLAGS) $(DEB_FLAGS) -c $< -o $@ + +$(OUT)/firmware.elf: $(OBJS) + $(TARGET_LD) $(LDFLAGS) -T $(FIRMWARE_DIR)/utils/tumbl.ld-script -o $@ $(OBJS) + +$(OUT)/bin2mem: $(FIRMWARE_DIR)/utils/bin2mem.c + gcc $< -o $@ + +.PHONY: re-firmware +re-firmware $(REQ_FIRMWARE): $(REQ_PKG) $(OUT)/bin2mem $(OUT)/firmware.elf + $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .text -S $(OUT)/imem.bin + $(TARGET_OBJCOPY) -O binary $(OUT)/firmware.elf -j .data -S $(OUT)/dmem.bin + $(TARGET_OBJDUMP) -DSCz $(OUT)/firmware.elf > $(OUT)/firmware.lst + cd $(OUT); \ + $(TARGET_OBJDUMP) -b binary -mmbtumbl -EB -D imem.bin | sed -e 's/.data/.text/' > imem.asm + +#=============================================================================== + +.PHONY: clean +clean: + rm -rf $(OUT) + +.PHONY: firmware +firmware: $(REQ_FIRMWARE) + +.PHONY: install-tumbl +install-tumbl: $(USB_SENDHEX) $(BUILDDIR)/imem.bin $(BUILDDIR)/dmem.bin + $(USB_SENDHEX) -d $(USB_APP_VID_PID) -c 0xF100 -a 0x0001 + $(USB_SENDHEX) -d $(USB_APP_VID_PID) -t 3 -s 0x00000000 -f binary $(BUILDDIR)/imem.bin + $(USB_SENDHEX) -d $(USB_APP_VID_PID) -t 3 -s 0x00001000 -f binary $(BUILDDIR)/dmem.bin + $(USB_SENDHEX) -d $(USB_APP_VID_PID) -c 0xF100 -a 0x0000 + +# imem +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80000000 -l 0x200 -f dump -u - +# dmem +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80001000 -l 0x200 -f dump -u - +# PC +# watch -d ./usb_sendhex -d 0x1669:0x1023 -t 4 -s 0x80003008 -l 0x4 -f dump -u - diff --git a/hw/tb/firmware-for-rx-crc/firmware.c b/hw/tb/firmware-for-rx-crc/firmware.c new file mode 100644 index 0000000..d21e02a --- /dev/null +++ b/hw/tb/firmware-for-rx-crc/firmware.c @@ -0,0 +1,70 @@ +/******************************************************************* + Components for embedded applications builded for + laboratory and medical instruments firmware + + firmware.c - Firmware to test Tumbl xmem bus access + + (C) 2001-2014 by Pavel Pisa pisa@cmp.felk.cvut.cz + (C) 2002-2014 by PiKRON Ltd. http://www.pikron.com + + *******************************************************************/ + +#include +#include "tumbl_addr.h" + +int32_t sin_res; +int32_t cos_res; + +void init_defvals(void) +{ +} + +#define LX_MASTER_DATA_OFFS 8 +#define PXMC_LXPWR_PWM_CYCLE 2500 + +void main(void) +{ + int i; + int grp_in = 0; + int grp_out = 0; + unsigned word_slot; + + unsigned lxpwr_header = 1; + unsigned lxpwr_words = 1 + 8 * 2 + 2; + unsigned lxpwr_chips = 2; + unsigned lxpwr_chip_pwm_cnt = 8; + + *FPGA_LX_MASTER_RESET = 1; + *FPGA_LX_MASTER_TX_REG = 0; + *FPGA_LX_MASTER_TX_CYCLE = PXMC_LXPWR_PWM_CYCLE; + + word_slot = LX_MASTER_DATA_OFFS + lxpwr_header + lxpwr_chip_pwm_cnt; + FPGA_LX_MASTER_RX[grp_in++] = (word_slot << 8) | lxpwr_words; + + word_slot = LX_MASTER_DATA_OFFS + 0; + FPGA_LX_MASTER_RX[grp_in++] = (word_slot << 8) | lxpwr_words; + + FPGA_LX_MASTER_RX[grp_in++] = 0x0000; + + for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++) + FPGA_LX_MASTER_TX[i] = 0; + + word_slot = LX_MASTER_DATA_OFFS + lxpwr_header + lxpwr_chip_pwm_cnt; + FPGA_LX_MASTER_TX[grp_out++] = (word_slot << 8) | lxpwr_words; + FPGA_LX_MASTER_TX[word_slot] = 0xc100 | (lxpwr_words - 1); + + word_slot = LX_MASTER_DATA_OFFS + 0; + FPGA_LX_MASTER_TX[grp_out++] = (word_slot << 8) | lxpwr_words; + FPGA_LX_MASTER_TX[word_slot] = 0xc100 | (lxpwr_words - 1); + + FPGA_LX_MASTER_TX[grp_out++] = 0x0000; + + *FPGA_LX_MASTER_RESET = 0; + *FPGA_LX_MASTER_TX_CYCLE = PXMC_LXPWR_PWM_CYCLE; + + + while (1) { + *FPGA_LX_MASTER_TX_PWM0 = *FPGA_LX_MASTER_TX_PWM0 + 1; + asm volatile("": : : "memory"); + } +} diff --git a/hw/tb/firmware-for-rx-crc/start.S b/hw/tb/firmware-for-rx-crc/start.S new file mode 100644 index 0000000..065542f --- /dev/null +++ b/hw/tb/firmware-for-rx-crc/start.S @@ -0,0 +1,29 @@ +/* LX ROCON firmware reduced startup file */ + +.globl _main +.align 2 + +_main: + + /* Stack pointer */ + addi r1, r0, 0xFFC + + /* reset data */ + addi r6, r0, _sdata + addi r7, r0, _edata + rsub r18, r6, r7 + brci le, r18, .Lenddata +.Lloopdata: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + brci gt, r18, .Lloopdata +.Lenddata: + /* Init default values */ + brli r15, init_defvals + + /* Run program */ + brli r15, main + + /* End of program */ + halt 0 diff --git a/hw/tb/firmware-for-rx-crc/tumbl_addr.h b/hw/tb/firmware-for-rx-crc/tumbl_addr.h new file mode 100644 index 0000000..649858e --- /dev/null +++ b/hw/tb/firmware-for-rx-crc/tumbl_addr.h @@ -0,0 +1,85 @@ +#ifndef _TUMBL_ADDR_H +#define _TUMBL_ADDR_H + +#include + +#ifndef IOPORT32BIT + #define IO32ADDR(_val) ((volatile uint32_t *)(_val)) +#endif /*IOPORT32BIT*/ + +#define FPGA_IRC_BASE 0x00002000 + +#define FPGA_IRC0 IO32ADDR(FPGA_IRC_BASE+0x0000) +#define FPGA_IRC1 IO32ADDR(FPGA_IRC_BASE+0x0008) +#define FPGA_IRC2 IO32ADDR(FPGA_IRC_BASE+0x0010) +#define FPGA_IRC3 IO32ADDR(FPGA_IRC_BASE+0x0018) +#define FPGA_IRC4 IO32ADDR(FPGA_IRC_BASE+0x0020) +#define FPGA_IRC5 IO32ADDR(FPGA_IRC_BASE+0x0028) +#define FPGA_IRC6 IO32ADDR(FPGA_IRC_BASE+0x0030) +#define FPGA_IRC7 IO32ADDR(FPGA_IRC_BASE+0x0038) + +#define FPGA_FNCAPPROX_BASE 0x00003000 + +#define FPGA_FNCAPPROX IO32ADDR(FPGA_FNCAPPROX_BASE) +#define FPGA_FNCAPPROX_RECI IO32ADDR(FPGA_FNCAPPROX_BASE+0x04) +#define FPGA_FNCAPPROX_SIN IO32ADDR(FPGA_FNCAPPROX_BASE+0x08) +#define FPGA_FNCAPPROX_COS IO32ADDR(FPGA_FNCAPPROX_BASE+0x0c) + +#define FPGA_LX_MASTER_BASE 0x00004000 + +#define FPGA_LX_MASTER_TX IO32ADDR(FPGA_LX_MASTER_BASE+0x0000) + +/* pwm_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) + chan; */ + +#define FPGA_LX_MASTER_TX_PWM0 (FPGA_LX_MASTER_TX+9) +#define FPGA_LX_MASTER_TX_PWM1 (FPGA_LX_MASTER_TX+10) +#define FPGA_LX_MASTER_TX_PWM2 (FPGA_LX_MASTER_TX+11) +#define FPGA_LX_MASTER_TX_PWM3 (FPGA_LX_MASTER_TX+12) +#define FPGA_LX_MASTER_TX_PWM4 (FPGA_LX_MASTER_TX+13) +#define FPGA_LX_MASTER_TX_PWM5 (FPGA_LX_MASTER_TX+14) +#define FPGA_LX_MASTER_TX_PWM6 (FPGA_LX_MASTER_TX+15) +#define FPGA_LX_MASTER_TX_PWM7 (FPGA_LX_MASTER_TX+16) + +#define FPGA_LX_MASTER_TX_PWM8 (FPGA_LX_MASTER_TX+18) +#define FPGA_LX_MASTER_TX_PWM9 (FPGA_LX_MASTER_TX+19) +#define FPGA_LX_MASTER_TX_PWM10 (FPGA_LX_MASTER_TX+20) +#define FPGA_LX_MASTER_TX_PWM11 (FPGA_LX_MASTER_TX+21) +#define FPGA_LX_MASTER_TX_PWM12 (FPGA_LX_MASTER_TX+22) +#define FPGA_LX_MASTER_TX_PWM13 (FPGA_LX_MASTER_TX+23) +#define FPGA_LX_MASTER_TX_PWM14 (FPGA_LX_MASTER_TX+24) +#define FPGA_LX_MASTER_TX_PWM15 (FPGA_LX_MASTER_TX+25) + +#define FPGA_LX_MASTER_RX IO32ADDR(FPGA_LX_MASTER_BASE+0x0800) + +/* rec_reg += LX_MASTER_DATA_OFFS + 1 + (chan >> 3) * 3 + chan * 2; */ + +#define FPGA_LX_MASTER_RX_ADC0 (FPGA_LX_MASTER_RX+9) +#define FPGA_LX_MASTER_RX_ADC1 (FPGA_LX_MASTER_RX+11) +#define FPGA_LX_MASTER_RX_ADC2 (FPGA_LX_MASTER_RX+13) +#define FPGA_LX_MASTER_RX_ADC3 (FPGA_LX_MASTER_RX+15) +#define FPGA_LX_MASTER_RX_ADC4 (FPGA_LX_MASTER_RX+17) +#define FPGA_LX_MASTER_RX_ADC5 (FPGA_LX_MASTER_RX+19) +#define FPGA_LX_MASTER_RX_ADC6 (FPGA_LX_MASTER_RX+21) +#define FPGA_LX_MASTER_RX_ADC7 (FPGA_LX_MASTER_RX+23) + +#define FPGA_LX_MASTER_RX_VIN (FPGA_LX_MASTER_RX+25) + +#define FPGA_LX_MASTER_RX_ADC8 (FPGA_LX_MASTER_RX+28) +#define FPGA_LX_MASTER_RX_ADC9 (FPGA_LX_MASTER_RX+30) +#define FPGA_LX_MASTER_RX_ADC10 (FPGA_LX_MASTER_RX+32) +#define FPGA_LX_MASTER_RX_ADC11 (FPGA_LX_MASTER_RX+34) +#define FPGA_LX_MASTER_RX_ADC12 (FPGA_LX_MASTER_RX+36) +#define FPGA_LX_MASTER_RX_ADC13 (FPGA_LX_MASTER_RX+38) +#define FPGA_LX_MASTER_RX_ADC14 (FPGA_LX_MASTER_RX+40) +#define FPGA_LX_MASTER_RX_ADC15 (FPGA_LX_MASTER_RX+42) + +#define FPGA_LX_MASTER_CTRL IO32ADDR(FPGA_LX_MASTER_BASE+0x1000) + +#define FPGA_LX_MASTER_RESET (FPGA_LX_MASTER_CTRL+0) +#define FPGA_LX_MASTER_TX_REG (FPGA_LX_MASTER_CTRL+1) +#define FPGA_LX_MASTER_TX_WDOG (FPGA_LX_MASTER_CTRL+2) +#define FPGA_LX_MASTER_TX_CYCLE (FPGA_LX_MASTER_CTRL+3) +#define FPGA_LX_MASTER_RX_REG (FPGA_LX_MASTER_CTRL+4) +#define FPGA_LX_MASTER_RX_DDIV (FPGA_LX_MASTER_CTRL+5) + +#endif /* _TUMBL_ADDR_H */ diff --git a/hw/tb/firmware-for-rx-crc/utils b/hw/tb/firmware-for-rx-crc/utils new file mode 120000 index 0000000..ab3869e --- /dev/null +++ b/hw/tb/firmware-for-rx-crc/utils @@ -0,0 +1 @@ +../../../submodule/tumbl/utils \ No newline at end of file diff --git a/hw/tb/lx_rocon-rx-crc.gtkw b/hw/tb/lx_rocon-rx-crc.gtkw new file mode 100644 index 0000000..04a0247 --- /dev/null +++ b/hw/tb/lx_rocon-rx-crc.gtkw @@ -0,0 +1,51 @@ +[*] +[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI +[*] Sun Feb 22 10:42:19 2015 +[*] +[dumpfile] "/home/pi/repo/ulan/lx-rocon-2/hw/tb/test-rocon.ghw" +[dumpfile_mtime] "Sun Feb 22 10:41:28 2015" +[dumpfile_size] 3402518 +[savefile] "/home/pi/repo/ulan/lx-rocon-2/hw/tb/lx_rocon-rx-crc.gtkw" +[timestart] 0 +[size] 1551 911 +[pos] -1 -1 +*-26.000000 32200000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.lx_rocon_top_tb. +[treeopen] top.lx_rocon_top_tb.uut. +[treeopen] top.lx_rocon_top_tb.uut.memory_bus_lxmaster. +[sst_width] 224 +[signals_width] 265 +[sst_expanded] 1 +[sst_vpaned_height] 264 +@28 +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.reset_i +top.lx_rocon_top_tb.s1_clk_out +top.lx_rocon_top_tb.s1_sync_out +top.lx_rocon_top_tb.s1_mosi +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_state_r +@22 +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[7:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_crc_out_s[0] +@28 +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_transmitter.lxmaster_sync_last_bit_r +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.sync_s +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.miso_s +@29 +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_state_r +@28 +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_we_s[1:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_we_s[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_we_s[0] +@22 +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[15:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[15] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[14] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[13] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[12] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[11] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[10] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[9] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[8] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.ram_data_i_s[0] +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[7:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_s[0] +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[7:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_reg_r[0] +@28 +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_error_int_r +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.bls_i[1:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.bls_i[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.bls_i[0] +@22 +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[10:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[10] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[9] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[8] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.address_i[0] +#{top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[15:0]} top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[15] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[14] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[13] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[12] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[11] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[10] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[9] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[8] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[7] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[6] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[5] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[4] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[3] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[2] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[1] top.lx_rocon_top_tb.uut.memory_bus_lxmaster.data_i[0] +@28 +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.reset_reg_r +top.lx_rocon_top_tb.uut.memory_bus_lxmaster.master_receiver.lxmaster_crc_error_r +[pattern_trace] 1 +[pattern_trace] 0 diff --git a/hw/tb/lx_rocon_top_tb.vhd b/hw/tb/lx_rocon_top_tb.vhd index f8e64ed..a9ecdf3 100644 --- a/hw/tb/lx_rocon_top_tb.vhd +++ b/hw/tb/lx_rocon_top_tb.vhd @@ -113,6 +113,9 @@ ARCHITECTURE behavior OF lx_rocon_top_tb IS signal s1_mosi : std_logic := '1'; signal s1_sync_out : std_logic := '1'; + signal s1_data : std_logic := '1'; + signal s1_sync_in_prev : std_logic := '1'; + --BiDirs signal data : std_logic_vector(31 downto 0); @@ -267,4 +270,17 @@ BEGIN end process; + s1_clk_in <= s1_clk_out; + + connect_s1_process : process + begin + wait until s1_clk_out'event and s1_clk_out = '0'; + wait for 10 ns; + + s1_data <= s1_mosi; + s1_miso <= s1_data; + s1_sync_in <= not s1_sync_out or s1_sync_in_prev; + s1_sync_in_prev <= not s1_sync_out; + end process; + END; -- 2.39.2