From e7e8bbb214cba469c7f8736efd732072fe74f5d2 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Wed, 31 Dec 2014 09:19:09 +0100 Subject: [PATCH] Update Tumbl and test of concurrent access. Signed-off-by: Pavel Pisa --- hw/tb/lx_tumbl_tb.vhd | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/tb/lx_tumbl_tb.vhd b/hw/tb/lx_tumbl_tb.vhd index 65bde9f..dccefe1 100644 --- a/hw/tb/lx_tumbl_tb.vhd +++ b/hw/tb/lx_tumbl_tb.vhd @@ -146,15 +146,35 @@ BEGIN end process; - events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2) + --events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2) + --begin + -- -- Simulate externall access to xmem bus shared with Tumbl + -- if cycle_cnt >= 46 and cycle_cnt <= 47 then + -- -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then + -- delay_access_s <= '1'; + -- else + -- delay_access_s <= '0'; + -- end if; + --end process; + + events_process: process begin - -- Simulate externall access to xmem bus shared with Tumbl - if cycle_cnt >= 47 and cycle_cnt <= 48 then - -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then - delay_access_s <= '1'; - else - delay_access_s <= '0'; - end if; + + wait until clk_cpu'event and clk_cpu = '1' and imem_ready_s = '1'; + + -- Simulate external master accesses to Tumbl shared xmem bus + xmem_loop: loop + wait until clk_cpu'event and clk_cpu = '1'; + wait until clk_cpu'event and clk_cpu = '1'; + wait until clk_cpu'event and clk_cpu = '1'; + wait until clk_cpu'event and clk_cpu = '1'; + wait until clk_cpu'event and clk_cpu = '1'; + delay_access_s <= transport '1' after 2 ns; + wait until clk_cpu'event and clk_cpu = '1'; + wait until clk_cpu'event and clk_cpu = '1'; + delay_access_s <= transport '0' after 2 ns; + end loop xmem_loop; + end process; -- Enable xmem clken only when bus available for Tumbl -- 2.39.2