From cd7ba0f0ca8e9fb66487f0e29d133867b928bcd9 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 23 Nov 2014 22:29:46 +0100 Subject: [PATCH] RoCoN: move Master RX ISR to appl_pxmc.c which allows to use it for PXMC timing. When PXMC_ROCON_TIMED_BY_RX_DONE is defined in appl_defs.h then whole PXMC controller and coordinated movement trimming is driven by by LX Master receive from LXPWR done event. Signed-off-by: Pavel Pisa --- sw/app/rocon/appl_defs.h | 28 ++++++++-- sw/app/rocon/appl_pxmc.c | 108 +++++++++++++++++++++++++++++++++++++- sw/app/rocon/appl_tests.c | 105 +++--------------------------------- 3 files changed, 139 insertions(+), 102 deletions(-) diff --git a/sw/app/rocon/appl_defs.h b/sw/app/rocon/appl_defs.h index 2971681..e6594bb 100644 --- a/sw/app/rocon/appl_defs.h +++ b/sw/app/rocon/appl_defs.h @@ -132,6 +132,21 @@ int usb_app_fill_serial_number(uint32_t ul_sn); int appl_global_action(int action_code); +/* Configuration of LX MASTER to LXPWR board */ +#define PXMC_ROCON_TIMED_BY_RX_DONE 1 + +#define ROCON_RX_TIM LPC_TIM2 +#define ROCON_RX_IRQn TIMER2_IRQn + +IRQ_HANDLER_FNC(pxmc_rocon_rx_done_isr); +int pxmc_rocon_rx_done_isr_setup(irq_handler_t rx_done_isr_handler); + +extern volatile void *pxmc_rocon_rx_data_hist_buff; +extern volatile void *pxmc_rocon_rx_data_hist_buff_end; +extern uint32_t pxmc_rocon_rx_cycle_time; +extern uint32_t pxmc_rocon_rx_irq_latency; +extern uint32_t pxmc_rocon_rx_irq_latency_max; + /* LPC Quadrature encoder events processing */ struct lpc_qei_state_t; void pxmc_lpc_qei_callback_index(struct lpc_qei_state_t *qst, void *context); @@ -148,16 +163,23 @@ int pxmc_process_state_check(unsigned long *pbusy_bits, long pxmc_sfi_spent_time_max; + int pxmc_initialize(void); int pxmc_done(void); int pxmc_coordmv_process(void); void pxmc_sfi_isr(void); void do_pxmc_coordmv(void); +#ifndef PXMC_ROCON_TIMED_BY_RX_DONE + #define PXMC_APPL_RUN_AT_FAST_SFI_ENTRIES \ + pxmc_sfi_isr(); \ + do_pxmc_coordmv(); +#else /*PXMC_ROCON_TIMED_BY_RX_DONE*/ + #define PXMC_APPL_RUN_AT_FAST_SFI_ENTRIES +#endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/ + #define APPL_RUN_AT_FAST_SFI do { \ - pxmc_sfi_isr(); \ - do_pxmc_coordmv(); \ - /*rocon_sfi_isr();*/ \ + PXMC_APPL_RUN_AT_FAST_SFI_ENTRIES \ ; \ } while(0) diff --git a/sw/app/rocon/appl_pxmc.c b/sw/app/rocon/appl_pxmc.c index 7fc9fea..02d85b7 100644 --- a/sw/app/rocon/appl_pxmc.c +++ b/sw/app/rocon/appl_pxmc.c @@ -27,6 +27,8 @@ #include #include #include +#include +#include #include "appl_defs.h" #include "appl_fpga.h" @@ -704,6 +706,100 @@ pxmc_rocon_pwm_dc_out(pxmc_state_t *mcs) return 0; } +volatile void *pxmc_rocon_rx_data_hist_buff; +volatile void *pxmc_rocon_rx_data_hist_buff_end; + +uint32_t pxmc_rocon_rx_last_irq; +uint32_t pxmc_rocon_rx_cycle_time; +uint32_t pxmc_rocon_rx_irq_latency; +uint32_t pxmc_rocon_rx_irq_latency_max; + +IRQ_HANDLER_FNC(pxmc_rocon_rx_done_isr) +{ + uint32_t ir; + + ir = ROCON_RX_TIM->IR & LPC_TIM_IR_ALL_m; + ROCON_RX_TIM->IR = ir; + if (ir & LPC_TIM_IR_CR1INT_m) { + uint32_t cr0, cr1; + cr0 = ROCON_RX_TIM->CR0; + cr1 = ROCON_RX_TIM->CR1; + + pxmc_rocon_rx_cycle_time = cr1 - pxmc_rocon_rx_last_irq; + pxmc_rocon_rx_last_irq = cr1; + + hal_gpio_set_value(T2MAT0_PIN, 1); + hal_gpio_set_value(T2MAT1_PIN, 0); + hal_gpio_set_value(T2MAT0_PIN, 0); + + if (pxmc_rocon_rx_data_hist_buff >= pxmc_rocon_rx_data_hist_buff_end) + pxmc_rocon_rx_data_hist_buff = NULL; + + if (pxmc_rocon_rx_data_hist_buff != NULL) { + int i; + volatile uint32_t *pwm_reg = fpga_lx_master_transmitter_base + 8; + volatile uint32_t *rec_reg = fpga_lx_master_receiver_base + 8; + uint16_t *pbuf = (uint16_t *)pxmc_rocon_rx_data_hist_buff; + for (i = 0; i < 8; i++) { + *(pbuf++) = *(rec_reg++); + } + for (i = 0; i < 8; i++) { + *(pbuf++) = *(pwm_reg++); + } + pxmc_rocon_rx_data_hist_buff = pbuf; + } + + pxmc_rocon_rx_irq_latency = ROCON_RX_TIM->TC - cr1; + if (pxmc_rocon_rx_irq_latency > pxmc_rocon_rx_irq_latency_max) + pxmc_rocon_rx_irq_latency_max = pxmc_rocon_rx_irq_latency; + + #ifdef PXMC_ROCON_TIMED_BY_RX_DONE + pxmc_sfi_isr(); + do_pxmc_coordmv(); + #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/ + } + + return IRQ_HANDLED; +} + +int +pxmc_rocon_rx_done_isr_setup(irq_handler_t rx_done_isr_handler) +{ + + disable_irq(ROCON_RX_IRQn); + + hal_pin_conf_set(T2MAT0_PIN, PORT_CONF_GPIO_OUT_LO); + hal_pin_conf_set(T2MAT1_PIN, PORT_CONF_GPIO_OUT_LO); + hal_pin_conf(T2CAP0_PIN); + hal_pin_conf(T2CAP1_PIN); + + hal_gpio_direction_output(T2MAT0_PIN, 1); + hal_gpio_direction_output(T2MAT1_PIN, 0); + hal_gpio_set_value(T2MAT0_PIN, 0); + + /* Enable CLKOUT pin function, source CCLK, divide by 1 */ + LPC_SC->CLKOUTCFG = 0x0100; + + request_irq(ROCON_RX_IRQn, rx_done_isr_handler, 0, NULL,NULL); + + ROCON_RX_TIM->TCR = 0; + ROCON_RX_TIM->CTCR = 0; + ROCON_RX_TIM->PR = 0; /* Divide by 1 */ + + ROCON_RX_TIM->CCR = LPC_TIM_CCR_CAP0RE_m | LPC_TIM_CCR_CAP1FE_m | + LPC_TIM_CCR_CAP1I_m; + + ROCON_RX_TIM->EMR = __val2mfld(LPC_TIM_EMR_EMC0_m, LPC_TIM_EMR_NOP) | + __val2mfld(LPC_TIM_EMR_EMC1_m, LPC_TIM_EMR_NOP); + + ROCON_RX_TIM->MCR = 0; /* No IRQ on MRx */ + ROCON_RX_TIM->TCR = LPC_TIM_TCR_CEN_m; /* Enable timer counting */ + enable_irq(ROCON_RX_IRQn); /* Enable interrupt */ + + return 0; + +} + int pxmc_rocon_pwm_master_init(void) { @@ -711,6 +807,7 @@ pxmc_rocon_pwm_master_init(void) int grp_in = 0; int grp_out = 0; unsigned word_slot; + unsigned receiver_done_div = 1; #ifdef LXPWR_WITH_SIROLADC unsigned lxpwr_header = 1; unsigned lxpwr_words = 1 + 8 * 2 + 2; @@ -723,10 +820,14 @@ pxmc_rocon_pwm_master_init(void) unsigned lxpwr_chip_pwm_cnt = 8; #endif /*LXPWR_WITH_SIROLADC*/ + #ifdef PXMC_ROCON_TIMED_BY_RX_DONE + receiver_done_div = 5; + #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/ + *fpga_lx_master_reset = 1; *fpga_lx_master_transmitter_reg = 0; *fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */ - *fpga_lx_master_receiver_done_div = 1 << 8; + *fpga_lx_master_receiver_done_div = receiver_done_div << 8; for (i = 0; i < LX_MASTER_DATA_OFFS + lxpwr_words * lxpwr_chips; i++) fpga_lx_master_receiver_base[i] = 0; @@ -754,7 +855,7 @@ pxmc_rocon_pwm_master_init(void) *fpga_lx_master_reset = 0; *fpga_lx_master_transmitter_cycle = 2500; /* 50 MHz -> 20 kHz */ - *fpga_lx_master_receiver_done_div = 1 << 8; + *fpga_lx_master_receiver_done_div = receiver_done_div << 8; return 0; } @@ -1695,6 +1796,9 @@ int pxmc_initialize(void) //pxmc_rocon_pwm3ph_wr(mcs, 0, 0, 0); pxmc_rocon_pwm_master_init(); + #ifdef PXMC_ROCON_TIMED_BY_RX_DONE + pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr); + #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/ pxmc_main_list.pxml_cnt = 0; pxmc_dbg_hist = NULL; diff --git a/sw/app/rocon/appl_tests.c b/sw/app/rocon/appl_tests.c index e2deb07..387649e 100644 --- a/sw/app/rocon/appl_tests.c +++ b/sw/app/rocon/appl_tests.c @@ -273,112 +273,23 @@ int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) } #endif /*SDRAM_BASE*/ -#define LXPWR_RX_TIM LPC_TIM2 -#define LXPWR_RX_IRQn TIMER2_IRQn - -volatile void *lxpwr_rx_data_hist_buff; -volatile void *lxpwr_rx_data_hist_buff_end; - -uint32_t lxpwr_rx_last_irq; -uint32_t lxpwr_rx_cycle_time; -uint32_t lxpwr_rx_irq_latency; -uint32_t lxpwr_rx_irq_latency_max; - -IRQ_HANDLER_FNC(lxpwr_rx_done_isr) -{ - uint32_t ir; - - ir = LXPWR_RX_TIM->IR & LPC_TIM_IR_ALL_m; - LXPWR_RX_TIM->IR = ir; - if (ir & LPC_TIM_IR_CR1INT_m) { - uint32_t cr0, cr1; - cr0 = LXPWR_RX_TIM->CR0; - cr1 = LXPWR_RX_TIM->CR1; - - lxpwr_rx_cycle_time = cr1 - lxpwr_rx_last_irq; - lxpwr_rx_last_irq = cr1; - - hal_gpio_set_value(T2MAT0_PIN, 1); - hal_gpio_set_value(T2MAT1_PIN, 0); - hal_gpio_set_value(T2MAT0_PIN, 0); - - if (lxpwr_rx_data_hist_buff >= lxpwr_rx_data_hist_buff_end) - lxpwr_rx_data_hist_buff = NULL; - - if (lxpwr_rx_data_hist_buff != NULL) { - int i; - volatile uint32_t *pwm_reg = fpga_lx_master_transmitter_base + 8; - volatile uint32_t *rec_reg = fpga_lx_master_receiver_base + 8; - uint16_t *pbuf = (uint16_t *)lxpwr_rx_data_hist_buff; - for (i = 0; i < 8; i++) { - *(pbuf++) = *(rec_reg++); - } - for (i = 0; i < 8; i++) { - *(pbuf++) = *(pwm_reg++); - } - lxpwr_rx_data_hist_buff = pbuf; - } - - lxpwr_rx_irq_latency = LXPWR_RX_TIM->TC - cr1; - if (lxpwr_rx_irq_latency > lxpwr_rx_irq_latency_max) - lxpwr_rx_irq_latency_max = lxpwr_rx_irq_latency; - } - - return IRQ_HANDLED; -} - -int lxpwr_rx_done_isr_init(void) -{ - - disable_irq(LXPWR_RX_IRQn); - - hal_pin_conf_set(T2MAT0_PIN, PORT_CONF_GPIO_OUT_LO); - hal_pin_conf_set(T2MAT1_PIN, PORT_CONF_GPIO_OUT_LO); - hal_pin_conf(T2CAP0_PIN); - hal_pin_conf(T2CAP1_PIN); - - hal_gpio_direction_output(T2MAT0_PIN, 1); - hal_gpio_direction_output(T2MAT1_PIN, 0); - hal_gpio_set_value(T2MAT0_PIN, 0); - - /* Enable CLKOUT pin function, source CCLK, divide by 1 */ - LPC_SC->CLKOUTCFG = 0x0100; - - request_irq(LXPWR_RX_IRQn, lxpwr_rx_done_isr, 0, NULL,NULL); - - LXPWR_RX_TIM->TCR = 0; - LXPWR_RX_TIM->CTCR = 0; - LXPWR_RX_TIM->PR = 0; /* Divide by 1 */ - - LXPWR_RX_TIM->CCR = LPC_TIM_CCR_CAP0RE_m | LPC_TIM_CCR_CAP1FE_m | - LPC_TIM_CCR_CAP1I_m; - - LXPWR_RX_TIM->EMR = __val2mfld(LPC_TIM_EMR_EMC0_m, LPC_TIM_EMR_NOP) | - __val2mfld(LPC_TIM_EMR_EMC1_m, LPC_TIM_EMR_NOP); - - LXPWR_RX_TIM->MCR = 0; /* No IRQ on MRx */ - LXPWR_RX_TIM->TCR = LPC_TIM_TCR_CEN_m; /* Enable timer counting */ - enable_irq(LXPWR_RX_IRQn); /* Enable interrupt */ - - return 0; - -} - int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { - lxpwr_rx_data_hist_buff = NULL; - lxpwr_rx_done_isr_init(); - lxpwr_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS + + pxmc_rocon_rx_data_hist_buff = NULL; + #ifndef PXMC_ROCON_TIMED_BY_RX_DONE + pxmc_rocon_rx_done_isr_setup(pxmc_rocon_rx_done_isr); + #endif /*PXMC_ROCON_TIMED_BY_RX_DONE*/ + pxmc_rocon_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS + 0x80000); - lxpwr_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS; + pxmc_rocon_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS; return 0; } int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[]) { printf("lxpwrrx period %ld latency %ld max %ld\n", - (long)lxpwr_rx_cycle_time, (long)lxpwr_rx_irq_latency, - (long)lxpwr_rx_irq_latency_max); + (long)pxmc_rocon_rx_cycle_time, (long)pxmc_rocon_rx_irq_latency, + (long)pxmc_rocon_rx_irq_latency_max); return 0; } -- 2.39.2