library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

-- IRC bus interconnect: memory region for IRC

entity bus_irc is
	port
	(
		clk         : in std_logic;
		reset       : in std_logic;

		-- Address (needs just last 4 bits, rest is wired to CE)
		address     : in std_logic_vector(3 downto 0);
		ce          : in std_logic;

		-- Data bus
		data_in     : in std_logic; -- 1 bit input
		data_out    : out std_logic_vector(31 downto 0);

		-- Bus signals
		rd          : in std_logic;
		ta          : out std_logic;
		wr          : in std_logic;

		-- Signals for IRC
		irc1_a      : in std_logic;
		irc1_b      : in std_logic;
		irc1_index  : in std_logic;
		irc1_mark   : in std_logic;

		irc2_a      : in std_logic;
		irc2_b      : in std_logic;
		irc2_index  : in std_logic;
		irc2_mark   : in std_logic;

		irc3_a      : in std_logic;
		irc3_b      : in std_logic;
		irc3_index  : in std_logic;
		irc3_mark   : in std_logic;

		irc4_a      : in std_logic;
		irc4_b      : in std_logic;
		irc4_index  : in std_logic;
		irc4_mark   : in std_logic

	);
end bus_irc;

architecture Behavioral of bus_irc is

	-- Multiplexer signals
	signal irc1_out : std_logic_vector(31 downto 0);
	signal irc1_ta : std_logic;
	signal irc1_ce : std_logic_vector(1 downto 0);

	signal irc2_out : std_logic_vector(31 downto 0);
	signal irc2_ta : std_logic;
	signal irc2_ce : std_logic_vector(1 downto 0);

	signal irc3_out : std_logic_vector(31 downto 0);
	signal irc3_ta : std_logic;
	signal irc3_ce : std_logic_vector(1 downto 0);

	signal irc4_out : std_logic_vector(31 downto 0);
	signal irc4_ta : std_logic;
	signal irc4_ce : std_logic_vector(1 downto 0);

	-- IRC register
	component irc_register
	port
	(
		clk      : in std_logic;
		reset    : in std_logic;
		a0, b0   : in std_logic;
		index0   : in std_logic;
		mark0    : in std_logic;
		data_in  : in std_logic;
		data_out : out std_logic_vector(31 downto 0);
		ce       : in std_logic_vector(1 downto 0);
		rd       : in std_logic;
		ta       : out std_logic;
		wr       : in std_logic
	);
	end component;

begin

	-- IRC for first axis
	irc1: irc_register
	port map
	(
		clk => clk,
		reset => reset,
		a0 => irc1_a,
		b0 => irc1_b,
		index0 => irc1_index,
		mark0 => irc1_mark,
		data_in => data_in,
		data_out => irc1_out,
		ce => irc1_ce,
		rd => rd,
		ta => irc1_ta,
		wr => wr
	);

	-- IRC for second axis
	irc2: irc_register
	port map
	(
		clk => clk,
		reset => reset,
		a0 => irc2_a,
		b0 => irc2_b,
		index0 => irc2_index,
		mark0 => irc2_mark,
		data_in => data_in,
		data_out => irc2_out,
		ce => irc2_ce,
		rd => rd,
		ta => irc2_ta,
		wr => wr
	);

	-- IRC for thrid axis
	irc3: irc_register
	port map
	(
		clk => clk,
		reset => reset,
		a0 => irc3_a,
		b0 => irc3_b,
		index0 => irc3_index,
		mark0 => irc3_mark,
		data_in => data_in,
		data_out => irc3_out,
		ce => irc3_ce,
		rd => rd,
		ta => irc3_ta,
		wr => wr
	);

	-- IRC for fourth axis
	irc4: irc_register
	port map
	(
		clk => clk,
		reset => reset,
		a0 => irc4_a,
		b0 => irc4_b,
		index0 => irc4_index,
		mark0 => irc4_mark,
		data_in => data_in,
		data_out => irc4_out,
		ce => irc4_ce,
		rd => rd,
		ta => irc4_ta,
		wr => wr
	);

	-- Bus update
	memory_bus_update: process(ce, address, irc1_out, irc1_ta, irc2_out, irc2_ta,
	                           irc3_out, irc3_ta, irc4_out, irc4_ta)
	begin

		-- Reset signals
		irc1_ce <= "11";
		irc2_ce <= "11";
		irc3_ce <= "11";
		irc4_ce <= "11";

		ta <= '1';
		data_out <= (others => 'X');

		if ce = '0' then

			-- We have 4-bit address, and IRC module has 3 registers
			-- Higher bits choose which IRC module, lower bits are for registers of the module
			case address(3 downto 2) is
				when "00" =>
					irc1_ce <= address(1 downto 0);
					data_out <= irc1_out;
					ta <= irc1_ta;

				when "01" =>
					irc2_ce <= address(1 downto 0);
					data_out <= irc2_out;
					ta <= irc2_ta;

				when "10" =>
					irc3_ce <= address(1 downto 0);
					data_out <= irc3_out;
					ta <= irc3_ta;

				when "11" =>
					irc4_ce <= address(1 downto 0);
					data_out <= irc4_out;
					ta <= irc4_ta;

				when others =>
					data_out <= (others => 'X');

			end case;

		end if;

	end process;

end Behavioral;