library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.lx_rocon_pkg.all;

-- LX Master bus interconnect
entity bus_lxmaster is
	port
	(
		clk_i        : in std_logic;
		reset_i      : in std_logic;
		-- Data bus
		address_i    : in std_logic_vector(9 downto 0);
		next_ce_i    : in std_logic;
		data_i       : in std_logic_vector(15 downto 0);
		data_o       : out std_logic_vector(15 downto 0);
		--
		bls_i        : in std_logic_vector(1 downto 0);
		-- Signals for LX Master
		clock_i      : in std_logic;
		miso_i       : in std_logic;
		sync_i       : in std_logic;
		--
		clock_o      : out std_logic;
		mosi_o       : out std_logic;
		sync_o       : out std_logic
	);
end bus_lxmaster;

architecture Behavioral of bus_lxmaster is

	signal mem_en_s             : std_logic;
	signal mem_bls_s            : std_logic_vector(1 downto 0);
	signal mem_addr_s           : std_logic_vector(8 downto 0);
	signal mem_data_s           : std_logic_vector(15 downto 0);
	signal mem_out_s            : std_logic;
	signal mem_out_r            : std_logic;
	--
	signal state_o_s            : std_logic;
	signal state_o_r            : std_logic;
	--
	signal reset_reg_s          : std_logic;
	signal reset_reg_r          : std_logic;
	signal reset_reg_wr_s       : std_logic;
	--
	signal reset_s              : std_logic;
	signal ce_s                 : std_logic;
	--
	signal register_in_s        : std_logic;
	signal register_out_s       : std_logic;
	signal register_wr_s        : std_logic;

begin

master_transmitter: lxmaster_transmitter
	port map
	(
		clk_i            => clk_i,
		reset_i          => reset_s,
		-- Transmission
		clock_o          => clock_o,
		mosi_o           => mosi_o,
		sync_o           => sync_o,
		-- Register
		register_i       => register_in_s,
		register_o       => register_out_s,
		register_we_i    => register_wr_s,
		-- BRAM
		mem_clk_i        => clk_i,
		mem_en_i         => mem_en_s,
		mem_we_i         => mem_bls_s,
		mem_addr_i       => mem_addr_s,
		mem_data_i       => data_i,
		mem_data_o       => mem_data_s
	);


	reset_s <= reset_reg_r or reset_i;

wire_in:
	process(next_ce_i, ce_s, reset_reg_r, bls_i, address_i, mem_data_s, data_i, register_out_s)
	begin

		mem_en_s             <= '0';
		mem_out_s            <= '0';
		mem_bls_s            <= (others => '0');
		mem_addr_s           <= (others => '0');
		state_o_s            <= '0';
		register_wr_s        <= '0';
		reset_reg_s          <= '0';
		reset_reg_wr_s       <= '0';
		register_in_s        <= '0';

		-- Incoming bus request
		if next_ce_i = '1' then

			-- Mapping:
			-- 0 & xxxxxxxx - LX Master BRAM
			-- 1 & 00000000 - LX Master reset
			-- 1 & 00000001 - LX Master register
			-- 1 & 10 & xxxxxx - LX Prasoreceiver
			if address_i(9) = '0' then

				mem_addr_s    <= address_i(8 downto 0);
				mem_en_s      <= '1';
				mem_bls_s     <= bls_i;
				mem_out_s     <= '1';

			else

				if address_i(8 downto 1) = "00000000" then

					if address_i(0) = '0' then
						-- LX Master reset
						if bls_i(0) = '1' then
							reset_reg_s    <= data_i(0);
							reset_reg_wr_s <= '1';
						else
							-- Ugh, hack :-)
							state_o_s      <= reset_reg_r;
						end if;
					else
						-- LX Master register
						if bls_i(0) = '1' then
							register_in_s  <= data_i(0);
							register_wr_s  <= '1';
						else
							state_o_s      <= register_out_s;
						end if;
					end if;

				end if;
			end if;
		end if;

	end process;

wire_out:
	process(ce_s, mem_data_s, mem_out_r, state_o_r)
	begin

		data_o <= (others => '0');

		if ce_s = '1' then
			if mem_out_r = '1' then
				data_o    <= mem_data_s;
			else
				data_o(0) <= state_o_r;
			end if;
		end if;

	end process;

update:
	process
	begin
		wait until clk_i'event and clk_i= '1';
		ce_s      <= next_ce_i;
		mem_out_r <= mem_out_s;
		state_o_r <= state_o_s;

		if reset_i = '1' then
			reset_reg_r <= '1';
		elsif reset_reg_wr_s = '1' then
			reset_reg_r <= reset_reg_s;
		end if;

	end process;

end Behavioral;