hw/tb/lx_tumbl_tb.vhd

   1 LIBRARY ieee;
   2 USE ieee.std_logic_1164.ALL;
   3 USE ieee.numeric_std.all;
   4
   5 LIBRARY std;
   6 USE std.textio.all;
   7
   8 USE work.mbl_pkg.all;
   9 USE work.lx_rocon_pkg.all;
  10
  11
  12
  13 ENTITY lx_tumbl_tb IS
  14 END lx_tumbl_tb;
  15
  16 ARCHITECTURE behavior OF lx_tumbl_tb IS
  17
  18         --Clock signals
  19         signal clk_cpu        : std_logic := '0';
  20         signal clk_50m        : std_logic := '0';
  21         -- Clock period definitions
  22         --constant clk_period_cpu : time := 13.8 ns;
  23         constant clk_period_50m : time := 20 ns;
  24         constant cycle_cnt_limit : natural := 2**20 - 1;
  25         signal cycle_cnt      : integer range 0 to cycle_cnt_limit;
  26
  27         signal tumbl_reset_s  : std_logic := '1';
  28
  29         -- Internal memory signals
  30         signal imem_en_s      : std_logic := '0';
  31         signal dmem_en_s      : std_logic := '0';
  32
  33         signal imem_we_s      : std_logic_vector(3 downto 0) := "0000";
  34         signal dmem_we_s      : std_logic_vector(3 downto 0) := "0000";
  35
  36         signal imem_data_o_s  : std_logic_vector(31 downto 0);
  37         signal dmem_data_o_s  : std_logic_vector(31 downto 0);
  38
  39         signal imem_data_i_s  : std_logic_vector(31 downto 0);
  40         signal dmem_data_i_s  : std_logic_vector(31 downto 0);
  41
  42         signal imem_address_s : std_logic_vector(8 downto 0);
  43         signal dmem_address_s : std_logic_vector(9 downto 0);
  44
  45         signal xmemb_sel_s    : std_logic;
  46         signal xmemb_i_s      : DMEMB2CORE_Type;
  47         signal xmemb_o_s      : CORE2DMEMB_Type;
  48
  49         signal imem_ready_s   : std_logic := '0';
  50         signal imem_fill_addr_s : natural range 0 to 2**8-1 := 0;
  51
  52         -- Simulate special events and interactions
  53         signal delay_access_s : std_logic := '0';
  54         signal delay_access_r : std_logic := '0';
  55         signal delay_access_r2 : std_logic := '0';
  56
  57 BEGIN
  58         -- Instantiate the Unit Under Test (UUT)
  59    uut: lx_rocon_tumbl
  60         generic map
  61         (
  62                 IMEM_ABITS_g         => 9,
  63                 DMEM_ABITS_g         => 10,
  64                 --
  65                 USE_HW_MUL_g         => true,
  66                 USE_BARREL_g         => true,
  67                 COMPATIBILITY_MODE_g => false
  68         )
  69         port map
  70         (
  71                 clk_i        => clk_cpu,
  72                 rst_i        => tumbl_reset_s,
  73                 halt_i       => '0',
  74                 int_i        => '0',
  75                 trace_i      => '0',
  76                 trace_kick_i => '0',
  77
  78                 pc_o         => open,
  79                 halted_o     => open,
  80                 halt_code_o  => open,
  81
  82                 -- Internal memory (instruction)
  83                 imem_clk_i   => clk_cpu,
  84                 imem_en_i    => imem_en_s,
  85                 imem_we_i    => imem_we_s,
  86                 imem_addr_i  => imem_address_s,
  87                 imem_data_i  => imem_data_i_s,
  88                 imem_data_o  => imem_data_o_s,
  89
  90                 -- Internal memory (data)
  91                 dmem_clk_i   => clk_cpu,
  92                 dmem_en_i    => dmem_en_s,
  93                 dmem_we_i    => dmem_we_s,
  94                 dmem_addr_i  => dmem_address_s,
  95                 dmem_data_i  => dmem_data_i_s,
  96                 dmem_data_o  => dmem_data_o_s,
  97
  98                 -- External memory bus
  99                 xmemb_sel_o  => xmemb_sel_s,
 100                 xmemb_i      => xmemb_i_s,
 101                 xmemb_o      => xmemb_o_s
 102         );
 103
 104         clk_cpu <= clk_50m;
 105         xmemb_i_s.int <= '0'; -- No interrupt
 106
 107         setup_process :process
 108         begin
 109                 wait until clk_cpu'event and clk_cpu = '1';
 110                 if cycle_cnt < cycle_cnt_limit and imem_ready_s = '1' then
 111                         cycle_cnt <= cycle_cnt + 1;
 112                 end if;
 113
 114                 if cycle_cnt < 8 then
 115                         tumbl_reset_s <= '1';
 116                 else
 117                         tumbl_reset_s <= '0';
 118                 end if;
 119         end process;
 120
 121         setup_imem_process : process
 122                 file imem_file : text open READ_MODE is "imem.bits";
 123                 variable my_line : LINE;
 124                 variable bits_line : LINE;
 125                 variable mem_location : bit_vector(31 downto 0);
 126         begin
 127                 wait until clk_50m'event and clk_50m = '1';
 128
 129                 if endfile(imem_file) then
 130                         if imem_ready_s = '0' then
 131                                 write(my_line, string'("reading imem complete"));
 132                                 writeline(output, my_line);
 133                         end if;
 134                         imem_ready_s <= '1';
 135                         imem_we_s <= "0000";
 136                         imem_en_s <= '0';
 137                 else
 138                         imem_address_s <= std_logic_vector(to_unsigned(imem_fill_addr_s, 9));
 139                         readline(imem_file, bits_line);
 140                         read(bits_line, mem_location);
 141                         imem_data_i_s <= to_stdLogicVector(mem_location);
 142                         imem_we_s <= "1111";
 143                         imem_en_s <= '1';
 144                         imem_fill_addr_s <= imem_fill_addr_s + 1;
 145                 end if;
 146
 147         end process;
 148
 149         events_process: process(cycle_cnt, xmemb_sel_s, delay_access_r, delay_access_r2)
 150         begin
 151                 -- Simulate externall access to xmem bus shared with Tumbl
 152                 if cycle_cnt >= 33 and cycle_cnt <= 33 then
 153                 -- if xmemb_sel_s = '1' and (delay_access_r = '0' or delay_access_r2 = '0') then
 154                         delay_access_s <= '1';
 155                 else
 156                         delay_access_s <= '0';
 157                 end if;
 158         end process;
 159
 160         -- Enable xmem clken only when bus available for Tumbl
 161         xmemb_i_s.bus_taken <= delay_access_s;
 162         xmemb_i_s.bus_wait <= '0';
 163
 164         xmemb_process :process
 165                 variable xmemb_addr_v : std_logic_vector(14 downto 0);
 166                 variable my_line : LINE;
 167         begin
 168                 wait until clk_cpu'event and clk_cpu = '1';
 169
 170                 xmemb_i_s.data  <= (others => 'X');
 171
 172                 xmemb_addr_v := xmemb_o_s.addr;
 173
 174                 if xmemb_o_s.rd = '1' then
 175                         if delay_access_s = '1' then
 176                                 xmemb_i_s.data(31 downto 16) <= x"F0F0";
 177                         else
 178                                 xmemb_i_s.data(31 downto 16) <= x"ACCE";
 179                                 xmemb_i_s.data(15 downto 2) <= xmemb_addr_v(13 downto 0);
 180                                 xmemb_i_s.data(1 downto 0) <= "00";
 181                         end if;
 182
 183                         write(my_line, string'("@"));
 184                         write(my_line, cycle_cnt);
 185                         write(my_line, string'(" tumbl read @("));
 186                         write(my_line, to_bitvector(xmemb_o_s.addr));
 187                         write(my_line, string'(")"));
 188                         writeline(output, my_line);
 189                 end if;
 190
 191                 if xmemb_o_s.bls /= "0000" then
 192                         write(my_line, string'("@"));
 193                         write(my_line, cycle_cnt);
 194                         write(my_line, string'(" tumbl write "));
 195                         write(my_line, to_bitvector(xmemb_i_s.data));
 196                         write(my_line, string'(" -> @("));
 197                         write(my_line, to_bitvector(xmemb_o_s.addr));
 198                         write(my_line, string'(")"));
 199                         writeline(output, my_line);
 200                 end if;
 201
 202                 delay_access_r <= delay_access_s;
 203                 delay_access_r2 <= delay_access_r;
 204         end process;
 205
 206
 207         clk_50m_process :process
 208         begin
 209                 clk_50m <= '1';
 210                 wait for clk_period_50m/2;
 211                 clk_50m <= '0';
 212                 wait for clk_period_50m/2;
 213         end process;
 214
 215         -- Stimulus process
 216         stim_proc: process
 217         begin
 218                 -- External ModelSim script
 219                 wait;
 220         end process;
 221
 222 END;