From a426922b779e0def2722d6eadf11072b807c39ce Mon Sep 17 00:00:00 2001
From: Jan Novotny <caca@caca>
Date: Thu, 30 Apr 2015 14:18:27 +0200
Subject: [PATCH] extended memotry for 2 samples of sensor data

---
 hw/bus_sensor.vhd | 96 +++++++++++++++++++++++++++++++++++++++++++++++
 hw/sensor_mem.vhd | 63 +++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+)
 create mode 100644 hw/bus_sensor.vhd
 create mode 100644 hw/sensor_mem.vhd

diff --git a/hw/bus_sensor.vhd b/hw/bus_sensor.vhd
new file mode 100644
index 0000000..e0c99d8
--- /dev/null
+++ b/hw/bus_sensor.vhd
@@ -0,0 +1,96 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lx_dad_pkg.all;
+
+-- Connects sampling memory and SPI interface
+
+entity bus_sensor is
+	port
+	(
+		-- Clock
+		clk_i        : in std_logic;
+		-- Chip enable
+		ce_i         : in std_logic;
+		-- Global Reset
+		reset_i      : in std_logic;
+		-- Master CPU peripheral bus
+		bls_i        : in std_logic_vector(3 downto 0);
+		address_i    : in std_logic_vector(10 downto 0);
+		data_i       : in std_logic_vector(31 downto 0);
+		data_o       : out std_logic_vector(31 downto 0);
+
+		
+		-- Memory wiring for internal state automata use
+		ce_a_i   : in std_logic;
+		adr_a_i  : in std_logic_vector(10 downto 0);
+		bls_a_i  : in std_logic_vector(3 downto 0);
+		dat_a_i  : in std_logic_vector(31 downto 0)
+		-- Non bus signals
+		--
+		-- Add there external component signals
+  );
+end bus_sensor;
+
+architecture Behavioral of bus_sensor is
+
+	signal sensor_mem_ce_s   : std_logic;
+	signal sensor_mem_ce_r   : std_logic;
+	signal sensor_mem_bls_s  : std_logic_vector(3 downto 0);
+	signal sensor_mem_dout_s : std_logic_vector(31 downto 0);
+	
+begin
+
+
+
+
+sensor_mem_instance: sensor_mem
+	port map
+	(
+		-- Memory wiring for internal state automata use
+		clk_i  => clk_i,
+		ce_i   => ce_a_i,
+		adr_i  => adr_a_i,
+		bls_i  => bls_a_i,
+		dat_i  => dat_a_i,
+		dat_o  => open,
+		-- Memory wiring for Master CPU
+		clk_m  => clk_i,
+		en_m   => sensor_mem_ce_s,
+		we_m   => sensor_mem_bls_s,
+		addr_m => address_i(10 downto 0),
+		din_m  => data_i,
+		dout_m => sensor_mem_dout_s
+	);
+
+decoder_logic: process(ce_i, address_i, bls_i)
+        begin
+		sensor_mem_ce_s <= '0';
+		sensor_mem_bls_s <= (others => '0');
+
+		if ce_i = '1' then --and address_i(11 downto 10) = "00" then
+			sensor_mem_ce_s <= '1';
+			sensor_mem_bls_s <= bls_i;
+		end if;
+	end process;
+
+output_multiplexer: process(sensor_mem_ce_r, sensor_mem_dout_s)
+        begin
+		data_o <= (others => '0');
+
+		if sensor_mem_ce_r = '1' then
+			data_o <= sensor_mem_dout_s;
+		end if;
+	end process;
+
+sync_update:
+	process
+	begin
+		wait until clk_i = '1' and clk_i'event;
+
+		sensor_mem_ce_r <= sensor_mem_ce_s;
+	end process;
+
+
+end Behavioral;
diff --git a/hw/sensor_mem.vhd b/hw/sensor_mem.vhd
new file mode 100644
index 0000000..1604929
--- /dev/null
+++ b/hw/sensor_mem.vhd
@@ -0,0 +1,63 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.lx_dad_pkg.all;
+
+-- 8 kB memory for data read from sensor
+-- Can be accessed from the Master CPU
+
+entity sensor_mem is
+	port
+	(
+		-- Memory wiring for internal state automata use
+		clk_i  : in std_logic;
+		ce_i   : in std_logic;
+		adr_i  : in std_logic_vector(10 downto 0);
+		bls_i  : in std_logic_vector(3 downto 0);
+		dat_i  : in std_logic_vector(31 downto 0);
+		dat_o  : out std_logic_vector(31 downto 0);
+		-- Memory wiring for Master CPU
+		clk_m  : in std_logic;
+		en_m   : in std_logic;
+		we_m   : in std_logic_vector(3 downto 0);
+		addr_m : in std_logic_vector(10 downto 0);
+		din_m  : in std_logic_vector(31 downto 0);
+		dout_m : out std_logic_vector(31 downto 0)
+	);
+end sensor_mem;
+
+architecture rtl of sensor_mem is
+begin
+
+I_RAMB: xilinx_dualport_bram
+	generic map
+	(
+		we_width => 4,
+		byte_width => 8,
+		address_width => 11,
+		port_a_type => READ_FIRST,
+		port_b_type => READ_FIRST
+	)
+	port map
+	(
+		-- Internal state automata port
+		clka => clk_i,
+		rsta => '0',
+		ena => ce_i,
+		wea => bls_i,
+		addra => adr_i,
+		dina => dat_i,
+		douta => dat_o,
+
+		-- Master CPU port
+		clkb => clk_m,
+		rstb => '0',
+		enb => en_m,
+		web => we_m,
+		addrb => addr_m,
+		dinb => din_m,
+		doutb => dout_m
+	);
+
+end rtl;
\ No newline at end of file
-- 
2.39.2