From e3a10d6f062dbfa14226db07906050e587dbfe56 Mon Sep 17 00:00:00 2001 From: Martin Meloun Date: Sat, 21 Sep 2013 14:35:23 +0200 Subject: [PATCH] MBTumbl: More constraints Signed-off-by: Martin Meloun --- gas/config/tc-microblaze.c | 18 +++++++++++++++++- opcodes/microblaze-dis.c | 14 ++++++++++++++ opcodes/microblaze-opc.h | 9 +++++++++ opcodes/microblaze-opcm.h | 23 +++++++++++++++++++++-- 4 files changed, 61 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c index 3ab854fef..327a70b59 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c @@ -418,6 +418,7 @@ parse_reg (char * s, unsigned * reg) *reg = REG_MSR; return s + 4; } +#ifndef ARCH_mbtumbl else if (strncasecmp (s, "rear", 4) == 0) { *reg = REG_EAR; @@ -528,6 +529,7 @@ parse_reg (char * s, unsigned * reg) } return s; } +#endif else { if (TOLOWER (s[0]) == 'r') @@ -752,12 +754,15 @@ static bfd_boolean check_spl_reg (unsigned * reg) { if ((*reg == REG_MSR) || (*reg == REG_PC) +#ifndef ARCH_mbtumbl || (*reg == REG_EAR) || (*reg == REG_ESR) || (*reg == REG_FSR) || (*reg == REG_BTR) || (*reg == REG_EDR) || (*reg == REG_PID) || (*reg == REG_ZPR) || (*reg == REG_TLBX) || (*reg == REG_TLBLO) || (*reg == REG_TLBHI) || (*reg == REG_TLBSX) - || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM)) + || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM) +#endif + ) return TRUE; return FALSE; @@ -1040,7 +1045,10 @@ md_assemble (char * str) as_fatal (_("Cannot use special register with this instruction")); if (exp.X_op != O_constant) + { as_warn (_("Symbol used as immediate for shift instruction")); + immed = 0; + } else { output = frag_more (isize); @@ -1111,6 +1119,7 @@ md_assemble (char * str) output = frag_more (isize); break; +#ifndef ARCH_mbtumbl case INST_TYPE_RD_RFSL: if (strcmp (op_end, "")) op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ @@ -1204,6 +1213,7 @@ md_assemble (char * str) inst |= (immed << IMM_LOW) & RFSL_MASK; output = frag_more (isize); break; +#endif case INST_TYPE_R1: if (strcmp (op_end, "")) @@ -1223,6 +1233,7 @@ md_assemble (char * str) break; /* For tuqula insn...:) */ +#ifndef ARCH_mbtumbl case INST_TYPE_RD: if (strcmp (op_end, "")) op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ @@ -1239,6 +1250,7 @@ md_assemble (char * str) inst |= (reg1 << RD_LOW) & RD_MASK; output = frag_more (isize); break; +#endif case INST_TYPE_RD_SPECIAL: if (strcmp (op_end, "")) @@ -1260,6 +1272,7 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_MSR_MASK; else if (reg2 == REG_PC) immed = opcode->immval_mask | REG_PC_MASK; +#ifndef ARCH_mbtumbl else if (reg2 == REG_EAR) immed = opcode->immval_mask | REG_EAR_MASK; else if (reg2 == REG_ESR) @@ -1282,6 +1295,7 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_TLBHI_MASK; else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM)) immed = opcode->immval_mask | REG_PVR_MASK | reg2; +#endif else as_fatal (_("invalid value for special purpose register")); inst |= (reg1 << RD_LOW) & RD_MASK; @@ -1309,6 +1323,7 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_MSR_MASK; else if (reg1 == REG_PC) immed = opcode->immval_mask | REG_PC_MASK; +#ifndef ARCH_mbtumbl else if (reg1 == REG_EAR) immed = opcode->immval_mask | REG_EAR_MASK; else if (reg1 == REG_ESR) @@ -1331,6 +1346,7 @@ md_assemble (char * str) immed = opcode->immval_mask | REG_TLBHI_MASK; else if (reg1 == REG_TLBSX) immed = opcode->immval_mask | REG_TLBSX_MASK; +#endif else as_fatal (_("invalid value for special purpose register")); inst |= (reg2 << RA_LOW) & RA_MASK; diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c index bdbf8317d..eb215a4cd 100644 --- a/opcodes/microblaze-dis.c +++ b/opcodes/microblaze-dis.c @@ -64,6 +64,8 @@ get_field_imm5 (long instr) return (strdup (tmpstr)); } +#ifndef ARCH_mbtumbl + static char * get_field_rfsl (long instr) { @@ -83,6 +85,8 @@ get_field_imm15 (long instr) return (strdup (tmpstr)); } +#endif + static char * get_field_special (long instr, struct op_code_struct * op) { @@ -97,6 +101,7 @@ get_field_special (long instr, struct op_code_struct * op) case REG_PC_MASK : strcpy (spr, "pc"); break; +#ifndef ARCH_mbtumbl case REG_EAR_MASK : strcpy (spr, "ear"); break; @@ -142,7 +147,12 @@ get_field_special (long instr, struct op_code_struct * op) else strcpy (spr, "pc"); break; +#else + default : + strcpy (spr, "pc"); + break; } +#endif sprintf (tmpstr, "%s%s", register_prefix, spr); return (strdup (tmpstr)); @@ -263,12 +273,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) print_func (stream, "\t%s, %s, %s", get_field_rd (inst), get_field_r1(inst), get_field_imm5 (inst)); break; +#ifndef ARCH_mbtumbl case INST_TYPE_RD_RFSL: print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst)); break; case INST_TYPE_R1_RFSL: print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_rfsl (inst)); break; +#endif case INST_TYPE_RD_SPECIAL: print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_special (inst, op)); @@ -371,6 +383,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) case INST_TYPE_RD_R1_SPECIAL: print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); break; +#ifndef ARCH_mbtumbl case INST_TYPE_RD_IMM15: print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst)); break; @@ -381,6 +394,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) case INST_TYPE_RFSL: print_func (stream, "\t%s", get_field_rfsl (inst)); break; +#endif default: /* If the disassembler lags the instruction set. */ print_func (stream, "\tundecoded operands, inst is 0x%04x", (unsigned int) inst); diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 67102b2ba..51fc257c4 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -41,21 +41,30 @@ #define INST_TYPE_R1 12 /* New instn type for barrel shift imms. */ #define INST_TYPE_RD_R1_IMM5 13 + +#ifndef ARCH_mbtumbl + #define INST_TYPE_RD_RFSL 14 #define INST_TYPE_R1_RFSL 15 +#endif + /* New insn type for insn cache. */ #define INST_TYPE_RD_R1_SPECIAL 16 /* New insn type for msrclr, msrset insns. */ #define INST_TYPE_RD_IMM15 17 +#ifndef ARCH_mbtumbl + /* New insn type for tuqula rd - addik rd, r0, 42. */ #define INST_TYPE_RD 18 /* New insn type for t*put. */ #define INST_TYPE_RFSL 19 +#endif + #define INST_TYPE_NONE 25 diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index ab9e9eff7..55c2f17bc 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -36,7 +36,7 @@ enum microblaze_instr imm, rtsd, rtid, bri, brid, brlid, brai, braid, bralid, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, bgtid, bgei, bgeid, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi, - sbi, shi, swi, + sbi, shi, swi, halt, invalid_inst }; @@ -83,7 +83,12 @@ enum microblaze_instr_type { arithmetic_inst, logical_inst, mult_inst, div_inst, branch_inst, return_inst, immediate_inst, special_inst, memory_load_inst, - memory_store_inst, barrel_shift_inst, anyware_inst + memory_store_inst, barrel_shift_inst, +#ifndef ARCH_mbtumbl + anyware_inst, +#else + halt_inst +#endif }; #define INST_WORD_SIZE 4 @@ -93,6 +98,9 @@ enum microblaze_instr_type #define REG_PC_MASK 0x8000 #define REG_MSR_MASK 0x8001 + +#ifndef ARCH_mbtumbl + #define REG_EAR_MASK 0x8003 #define REG_ESR_MASK 0x8005 #define REG_FSR_MASK 0x8007 @@ -107,6 +115,8 @@ enum microblaze_instr_type #define REG_TLBHI_MASK 0x9004 #define REG_TLBSX_MASK 0x9005 +#endif + #define MIN_REGNUM 0 #define MAX_REGNUM 31 @@ -115,6 +125,9 @@ enum microblaze_instr_type #define REG_PC 32 /* PC. */ #define REG_MSR 33 /* Machine status reg. */ + +#ifndef ARCH_mbtumbl + #define REG_EAR 35 /* Exception reg. */ #define REG_ESR 37 /* Exception reg. */ #define REG_FSR 39 /* FPU Status reg. */ @@ -129,6 +142,8 @@ enum microblaze_instr_type #define REG_TLBHI 36868 /* MMU: TLB High reg. */ #define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */ +#endif + /* Alternate names for gen purpose regs. */ #define REG_SP 1 /* stack pointer. */ #define REG_ROSDP 2 /* read-only small data pointer. */ @@ -151,10 +166,14 @@ enum microblaze_instr_type /* Imm mask for barrel shifts. */ #define IMM5_MASK 0x0000001F +#ifndef ARCH_mbtumbl + /* FSL imm mask for get, put instructions. */ #define RFSL_MASK 0x000000F /* Imm mask for msrset, msrclr instructions. */ #define IMM15_MASK 0x00007FFF +#endif + #endif /* MICROBLAZE-OPCM */ -- 2.39.2