MBTumbl: Halt has only range between 0 - 31

[fpga/lx-cpu1/binutils-tumbl.git] / opcodes / microblaze-opc.h

diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 09ba7f2005af3eb46509c793984f84fd184bb5f9..f6c294fa28467c462f1412e089283a42c9873d89 100644 (file)
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -63,6 +63,11 @@
 /* New insn type for t*put.  */
 #define INST_TYPE_RFSL  19
 
+#else
+
+/* Halt instruction type */
+#define INST_TYPE_IMM5 20
+
 #endif
 
 #define INST_TYPE_NONE 25
@@ -94,6 +99,7 @@
 #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
 #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
 #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+#define OPCODE_MASK_H123A 0xFFFFFFE0 /* All but the last 5 bits */
 #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */  
 #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
 #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
@@ -419,7 +425,7 @@ struct op_code_struct
   {"necaputd",  INST_TYPE_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C000760, OPCODE_MASK_H34C, necaputd,  anyware_inst },
   {"tnecaputd", INST_TYPE_R2,    INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x4C0007E0, OPCODE_MASK_H34C, tnecaputd, anyware_inst },
 #else
-  {"halt",   INST_TYPE_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H12, halt, halt_inst },
+  {"halt",   INST_TYPE_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H123A, halt, halt_inst },
 #endif
   {"", 0, 0, 0, 0, 0, 0, 0, 0},
 };