enum microblaze_instr
{
- add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, cmpi,
+ add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, cmp, cmpu, cmpi, cmpui,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, muli,
bsll, bsra, bsrl, bslli, bsrai, bsrli, or, and, xor,
andn, sra, src, srl, sext8, sext16, mts, mfs, br, brd, brl,
bra, bral, beq, bne, blt, ble, bgt, bge, ori, andi, xori, andni,
imm, rts, rti, bri, brli, brai, brali, beqi, bnei, blti, blei, bgti,
bgei, lbu, lhu, lw, lwx, sb, sh, sw, swx, lbui, lhui, lwi,
- sbi, shi, swi, halt, it, itt, ite,
+ sbi, shi, swi, halt, it, itt, ite, itu, ittu, iteu, iti, itti, itei,
+ itui, ittui, iteui,
invalid_inst
};
#ifndef ARCH_mbtumbl
anyware_inst,
#else
- halt_inst,
- pseudo_inst
+ halt_inst
#endif
};
/* Tumbl conditions for it, itt, ite */
-#define COND_ALL 0
-#define COND_EQ 1
-#define COND_NE 2
-#define COND_LT 3
-#define COND_LE 4
-#define COND_GT 5
-#define COND_GE 6
+#define COND_EQ 0
+#define COND_NE 1
+#define COND_LT 2
+#define COND_LE 3
+#define COND_GT 4
+#define COND_GE 5
-#define COND_LOW 0
-#define COND_MASK 0x7
-
-#define COND_TYPE_MASK 0x18
-#define COND_TYPE_LOW 3
-
-#define COND_TYPE_ALL 0
-#define COND_TYPE_IT 1
-#define COND_TYPE_ITT 2
-#define COND_TYPE_ITE 3
+#define COND_LOW 21
+#define COND_MASK 0x00E00000
#endif