MBTumbl: Update ITxxx instructions to new format, add some macros that were disabled

[fpga/lx-cpu1/binutils-tumbl.git] / gas / config / tc-microblaze.c

diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 560215f936a47d3298efae550c1c4c2b055312d3..b2575c7f39d3eb084e09b151763e84df6eee58da 100644 (file)
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -104,11 +104,6 @@ static segT sdata_segment = 0;     /* Small data section.  */
 static segT sdata2_segment = 0; /* Small read-only section.  */
 static segT rodata_segment = 0; /* read-only section.  */
 
-/* Previous instruction (for pseudo instructions) */
-static char * last_output;
-static int last_inst;
-static int last_pseudo;
-
 /* Generate a symbol for stabs information.  */
 
 void
@@ -606,7 +601,7 @@ parse_cond (char * s, unsigned * cond)
       *cond = COND_GE;
       return s + 2;
     }
-  else 
+  else
     {
       as_bad (_("condition expected, but saw '%.6s'"), s);
       *cond = 0;
@@ -848,7 +843,7 @@ md_assemble (char * str)
   struct op_code_struct * opcode, *opcode1;
   char * output = NULL;
   int nlen = 0;
-  int pseudo = 0;
+  int cond = 0;
   int i;
   unsigned long inst, inst1;
   unsigned reg1;
@@ -895,12 +890,28 @@ md_assemble (char * str)
   switch (opcode->inst_type)
     {
     case INST_TYPE_RD_R1_R2:
-      if (strcmp (op_end, ""))
-        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+    case INST_TYPE_COND_R1_R2:
+      if (opcode->inst_type == INST_TYPE_COND_R1_R2)
+        {
+        cond = 1;
+        if (strcmp (op_end, ""))
+          op_end = parse_cond (op_end + 1, &reg1);  /* Get rd.  */
+        else
+          {
+            as_fatal (_("Error in statement syntax"));
+            reg1 = 0;
+          }
+        }
       else
         {
-          as_fatal (_("Error in statement syntax"));
-          reg1 = 0;
+        cond = 0;
+        if (strcmp (op_end, ""))
+          op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+        else
+          {
+            as_fatal (_("Error in statement syntax"));
+            reg1 = 0;
+          }
         }
       if (strcmp (op_end, ""))
         op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
@@ -918,23 +929,26 @@ md_assemble (char * str)
         }
 
       /* Check for spl registers.  */
-      if (check_spl_reg (& reg1))
+      if (!cond && check_spl_reg (& reg1))
         as_fatal (_("Cannot use special register with this instruction"));
       if (check_spl_reg (& reg2))
         as_fatal (_("Cannot use special register with this instruction"));
       if (check_spl_reg (& reg3))
         as_fatal (_("Cannot use special register with this instruction"));
 
+      if (cond)
+        inst |= (reg1 << COND_LOW) & COND_MASK;
+      else
+        inst |= (reg1 << RD_LOW) & RD_MASK;
+
       if (streq (name, "sub"))
        {
           /* sub rd, r1, r2 becomes rsub rd, r2, r1.  */
-          inst |= (reg1 << RD_LOW) & RD_MASK;
           inst |= (reg3 << RA_LOW) & RA_MASK;
           inst |= (reg2 << RB_LOW) & RB_MASK;
         }
       else
         {
-          inst |= (reg1 << RD_LOW) & RD_MASK;
           inst |= (reg2 << RA_LOW) & RA_MASK;
           inst |= (reg3 << RB_LOW) & RB_MASK;
         }
@@ -942,12 +956,28 @@ md_assemble (char * str)
       break;
 
     case INST_TYPE_RD_R1_IMM:
-      if (strcmp (op_end, ""))
-       op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+    case INST_TYPE_COND_R1_IMM:
+      if (opcode->inst_type == INST_TYPE_COND_R1_IMM)
+        {
+        cond = 1;
+        if (strcmp (op_end, ""))
+          op_end = parse_cond (op_end + 1, &reg1);  /* Get rd.  */
+        else
+          {
+            as_fatal (_("Error in statement syntax"));
+            reg1 = 0;
+          }
+        }
       else
-       {
-          as_fatal (_("Error in statement syntax"));
-          reg1 = 0;
+        {
+        cond = 0;
+        if (strcmp (op_end, ""))
+          op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+        else
+          {
+            as_fatal (_("Error in statement syntax"));
+            reg1 = 0;
+          }
         }
       if (strcmp (op_end, ""))
        op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
@@ -962,7 +992,7 @@ md_assemble (char * str)
        as_fatal (_("Error in statement syntax"));
 
       /* Check for spl registers.  */
-      if (check_spl_reg (& reg1))
+      if (!cond && check_spl_reg (& reg1))
        as_fatal (_("Cannot use special register with this instruction"));
       if (check_spl_reg (& reg2))
        as_fatal (_("Cannot use special register with this instruction"));
@@ -1065,7 +1095,10 @@ md_assemble (char * str)
               output[3] = INST_BYTE3 (inst1);
               output = frag_more (isize);
            }
-         inst |= (reg1 << RD_LOW) & RD_MASK;
+         if (cond)
+      inst |= (reg1 << COND_LOW) & COND_MASK;
+    else
+      inst |= (reg1 << RD_LOW) & RD_MASK;
          inst |= (reg2 << RA_LOW) & RA_MASK;
          inst |= (immed << IMM_LOW) & IMM_MASK;
        }
@@ -1305,43 +1338,6 @@ md_assemble (char * str)
       break;
 #else
 
-    case INST_TYPE_COND:
-      if (strcmp (op_end, ""))
-        op_end = parse_cond (op_end + 1, &reg1);  /* Get cond.  */
-      else
-      {
-        as_fatal (_("Error in statement syntax"));
-        reg1 = 0;
-      }
-
-      if (last_pseudo != 0 || last_output == NULL)
-      {
-        as_fatal (_("IT, ITT, ITE pseudo instructions must follow CMP or CMPU isntructions"));
-        return;
-      }
-
-      opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "cmp");
-      if ((opcode1 == NULL) || ((last_inst & opcode1->opcode_mask) != opcode1->bit_sequence))
-      {
-        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "cmpu");
-        if ((opcode1 == NULL) || ((last_inst & opcode1->opcode_mask) != opcode1->bit_sequence))
-        {
-          as_fatal (_("IT, ITT, ITE pseudo instructions must follow CMP or CMPU isntructions"));
-          return;
-        }
-      }
-
-      /* Modify last instruction */
-      last_inst |= (reg1 << COND_LOW) & COND_MASK;
-      last_inst |= opcode->bit_sequence;
-      last_output[0] = INST_BYTE0 (last_inst);
-      last_output[1] = INST_BYTE1 (last_inst);
-      last_output[2] = INST_BYTE2 (last_inst);
-      last_output[3] = INST_BYTE3 (last_inst);
-
-      /* Only one pseudo instruction follows */
-      pseudo = 1;
-      break;
 #endif
 
     case INST_TYPE_RD_SPECIAL:
@@ -1735,17 +1731,10 @@ md_assemble (char * str)
   if (strcmp (op_end, opcode->name) && strcmp (op_end, ""))
     as_warn (_("ignoring operands: %s "), op_end);
 
-  if (!pseudo)
-  {
-    output[0] = INST_BYTE0 (inst);
-    output[1] = INST_BYTE1 (inst);
-    output[2] = INST_BYTE2 (inst);
-    output[3] = INST_BYTE3 (inst);
-
-    last_output = output;
-    last_inst = inst;
-  }
-  last_pseudo = pseudo;
+  output[0] = INST_BYTE0 (inst);
+  output[1] = INST_BYTE1 (inst);
+  output[2] = INST_BYTE2 (inst);
+  output[3] = INST_BYTE3 (inst);
 
 #ifdef OBJ_ELF
   dwarf2_emit_insn (4);