bool
select BR2_ARM_CPU_HAS_VFPV3
+config BR2_ARM_CPU_HAS_FP_ARMV8
+ bool
+ select BR2_ARM_CPU_HAS_VFPV4
+
+config BR2_ARM_CPU_HAS_ARM
+ bool
+
+config BR2_ARM_CPU_HAS_THUMB
+ bool
+
+config BR2_ARM_CPU_HAS_THUMB2
+ bool
+
+config BR2_ARM_CPU_ARMV4
+ bool
+
+config BR2_ARM_CPU_ARMV5
+ bool
+
+config BR2_ARM_CPU_ARMV6
+ bool
+
+config BR2_ARM_CPU_ARMV7A
+ bool
+
+config BR2_ARM_CPU_ARMV7M
+ bool
+
+config BR2_ARM_CPU_ARMV8A
+ bool
+
choice
prompt "Target Architecture Variant"
- depends on BR2_arm || BR2_armeb
+ default BR2_cortex_a53 if BR2_ARCH_IS_64
default BR2_arm926t
help
Specific CPU variant to use
-config BR2_arm7tdmi
- bool "arm7tdmi"
-config BR2_arm720t
- bool "arm720t"
+if !BR2_ARCH_IS_64
+comment "armv4 cores"
config BR2_arm920t
bool "arm920t"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV4
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm922t
bool "arm922t"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV4
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_fa526
+ bool "fa526/626"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_ARMV4
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_strongarm
+ bool "strongarm sa110/sa1100"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_ARMV4
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+
+comment "armv5 cores"
config BR2_arm926t
bool "arm926t"
-config BR2_arm10t
- bool "arm10t"
-config BR2_arm1136jf_s_r0
- bool "arm1136jf_s rev0"
- select BR2_ARM_CPU_HAS_VFPV2
-config BR2_arm1136jf_s_r1
- bool "arm1136jf_s rev1"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV5
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_iwmmxt
+ bool "iwmmxt"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_ARMV5
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_xscale
+ bool "xscale"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV5
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+
+comment "armv6 cores"
+config BR2_arm1136j_s
+ bool "arm1136j-s"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV6
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_arm1136jf_s
+ bool "arm1136jf-s"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV6
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1176jz_s
bool "arm1176jz-s"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV6
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_arm1176jzf_s
bool "arm1176jzf-s"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV2
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV6
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_arm11mpcore
+ bool "mpcore"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ select BR2_ARM_CPU_HAS_THUMB
+ select BR2_ARM_CPU_ARMV6
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+
+comment "armv7a cores"
config BR2_cortex_a5
bool "cortex-A5"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a7
bool "cortex-A7"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a8
bool "cortex-A8"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV3
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a9
bool "cortex-A9"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_MAYBE_HAS_NEON
select BR2_ARM_CPU_MAYBE_HAS_VFPV3
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_cortex_a12
+ bool "cortex-A12"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_NEON
+ select BR2_ARM_CPU_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
config BR2_cortex_a15
bool "cortex-A15"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_NEON
select BR2_ARM_CPU_HAS_VFPV4
-config BR2_fa526
- bool "fa526/626"
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_cortex_a15_a7
+ bool "cortex-A15/A7 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_NEON
+ select BR2_ARM_CPU_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
+config BR2_cortex_a17
+ bool "cortex-A17"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_NEON
+ select BR2_ARM_CPU_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+config BR2_cortex_a17_a7
+ bool "cortex-A17/A7 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_NEON
+ select BR2_ARM_CPU_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
config BR2_pj4
bool "pj4"
+ select BR2_ARM_CPU_HAS_ARM
select BR2_ARM_CPU_HAS_VFPV3
-config BR2_strongarm
- bool "strongarm sa110/sa1100"
-config BR2_xscale
- bool "xscale"
-config BR2_iwmmxt
- bool "iwmmxt"
+ select BR2_ARM_CPU_ARMV7A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+
+comment "armv7m cores"
+config BR2_cortex_m3
+ bool "cortex-M3"
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7M
+config BR2_cortex_m4
+ bool "cortex-M4"
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7M
+endif # !BR2_ARCH_IS_64
+
+comment "armv8 cores"
+config BR2_cortex_a32
+ bool "cortex-A32"
+ depends on !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_ARM
+ select BR2_ARM_CPU_HAS_NEON
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_cortex_a35
+ bool "cortex-A35"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_cortex_a53
+ bool "cortex-A53"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_cortex_a57
+ bool "cortex-A57"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+config BR2_cortex_a57_a53
+ bool "cortex-A57/A53 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_cortex_a72
+ bool "cortex-A72"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+config BR2_cortex_a72_a53
+ bool "cortex-A72/A53 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+config BR2_cortex_a73
+ bool "cortex-A73"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_cortex_a73_a35
+ bool "cortex-A73/A35 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_cortex_a73_a53
+ bool "cortex-A73/A53 big.LITTLE"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_exynos_m1
+ bool "exynos-m1"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+config BR2_falkor
+ bool "falkor"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_qdf24xx
+ bool "qdf24xx"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
+if BR2_ARCH_IS_64
+config BR2_thunderx
+ bool "thunderx"
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+config BR2_thunderxt81
+ bool "thunderxt81"
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_thunderxt83
+ bool "thunderxt83"
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_thunderxt88
+ bool "thunderxt88"
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_thunderxt88p1
+ bool "thunderxt88p1"
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+endif # BR2_ARCH_IS_64
+config BR2_xgene1
+ bool "xgene1"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+
+if BR2_ARCH_IS_64
+comment "armv8.1a cores"
+config BR2_thunderx2t99
+ bool "thunderx2t99"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_thunderx2t99p1
+ bool "thunderx2t99p1"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+config BR2_vulcan
+ bool "vulcan"
+ select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64
+ select BR2_ARM_CPU_HAS_FP_ARMV8
+ select BR2_ARM_CPU_ARMV8A
+ select BR2_ARCH_HAS_MMU_OPTIONAL
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_7
+endif # BR2_ARCH_IS_64
endchoice
-config BR2_arm1136jf_s
- bool
- default BR2_arm1136jf_s_r0 || BR2_arm1136jf_s_r1
+config BR2_ARM_ENABLE_NEON
+ bool "Enable NEON SIMD extension support"
+ depends on BR2_ARM_CPU_MAYBE_HAS_NEON
+ select BR2_ARM_CPU_HAS_NEON
+ help
+ For some CPU cores, the NEON SIMD extension is optional.
+ Select this option if you are certain your particular
+ implementation has NEON support and you want to use it.
+
+config BR2_ARM_ENABLE_VFP
+ bool "Enable VFP extension support"
+ depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
+ select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
+ select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ help
+ For some CPU cores, the VFP extension is optional. Select
+ this option if you are certain your particular
+ implementation has VFP support and you want to use it.
choice
prompt "Target ABI"
- depends on BR2_arm || BR2_armeb
+ default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
default BR2_ARM_EABI
+ depends on BR2_arm || BR2_armeb
help
Application Binary Interface to use. The Application Binary
Interface describes the calling conventions (how arguments
config BR2_ARM_EABIHF
bool "EABIhf"
- depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2 || BR2_ARM_CPU_HAS_VFPV2
+ depends on BR2_ARM_CPU_HAS_VFPV2
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
endchoice
-config BR2_ARM_ENABLE_NEON
- bool "Enable NEON SIMD extension support"
- depends on BR2_ARM_CPU_MAYBE_HAS_NEON
- select BR2_ARM_CPU_HAS_NEON
- help
- For some CPU cores, the NEON SIMD extension is optional.
- Select this option if you are certain your particular
- implementation has NEON support and you want to use it.
-
choice
prompt "Floating point strategy"
- depends on BR2_ARM_EABI || BR2_ARM_EABIHF
+ default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
config BR2_ARM_FPU_VFPV2
bool "VFPv2"
- depends on BR2_ARM_CPU_HAS_VFPV2 || BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ depends on BR2_ARM_CPU_HAS_VFPV2
help
This option allows to use the VFPv2 floating point unit, as
- available in some ARMv6 processors (ARM1136JF-S,
- ARM1176JZF-S and ARM11 MPCore).
+ available in some ARMv5 processors (ARM926EJ-S) and some
+ ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11
+ MPCore).
Note that this option is also safe to use for newer cores
such as Cortex-A, because the VFPv3 and VFPv4 units are
config BR2_ARM_FPU_VFPV3
bool "VFPv3"
- depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
+ depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
config BR2_ARM_FPU_VFPV3D16
bool "VFPv3-D16"
- depends on BR2_ARM_CPU_HAS_VFPV3 || BR2_ARM_CPU_MAYBE_HAS_VFPV3
+ depends on BR2_ARM_CPU_HAS_VFPV3
help
This option allows to use the VFPv3 floating point unit, as
available in some ARMv7 processors (Cortex-A{8, 9}). This
config BR2_ARM_FPU_VFPV4
bool "VFPv4"
- depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
+ depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
config BR2_ARM_FPU_VFPV4D16
bool "VFPv4-D16"
- depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
+ depends on BR2_ARM_CPU_HAS_VFPV4
help
This option allows to use the VFPv4 floating point unit, as
available in some ARMv7 processors (Cortex-A{5, 7, 12,
config BR2_ARM_FPU_NEON_VFPV4
bool "NEON/VFPv4"
- depends on BR2_ARM_CPU_HAS_VFPV4 || BR2_ARM_CPU_MAYBE_HAS_VFPV4
+ depends on BR2_ARM_CPU_HAS_VFPV4
depends on BR2_ARM_CPU_HAS_NEON
help
This option allows to use both the VFPv4 and the NEON SIMD
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
+config BR2_ARM_FPU_FP_ARMV8
+ bool "FP-ARMv8"
+ depends on BR2_ARM_CPU_HAS_FP_ARMV8
+ help
+ This option allows to use the ARMv8 floating point unit.
+
+config BR2_ARM_FPU_NEON_FP_ARMV8
+ bool "NEON/FP-ARMv8"
+ depends on BR2_ARM_CPU_HAS_FP_ARMV8
+ depends on BR2_ARM_CPU_HAS_NEON
+ help
+ This option allows to use both the ARMv8 floating point unit
+ and the NEON SIMD unit for floating point operations.
+
+endchoice
+
+choice
+ prompt "ARM instruction set"
+ depends on BR2_arm || BR2_armeb
+
+config BR2_ARM_INSTRUCTIONS_ARM
+ bool "ARM"
+ depends on BR2_ARM_CPU_HAS_ARM
+ help
+ This option instructs the compiler to generate regular ARM
+ instructions, that are all 32 bits wide.
+
+config BR2_ARM_INSTRUCTIONS_THUMB
+ bool "Thumb"
+ depends on BR2_ARM_CPU_HAS_THUMB
+ # Thumb-1 and VFP are not compatible
+ depends on BR2_ARM_SOFT_FLOAT
+ help
+ This option instructions the compiler to generate Thumb
+ instructions, which allows to mix 16 bits instructions and
+ 32 bits instructions. This generally provides a much smaller
+ compiled binary size.
+
+comment "Thumb1 is not compatible with VFP"
+ depends on BR2_ARM_CPU_HAS_THUMB
+ depends on !BR2_ARM_SOFT_FLOAT
+
+config BR2_ARM_INSTRUCTIONS_THUMB2
+ bool "Thumb2"
+ depends on BR2_ARM_CPU_HAS_THUMB2
+ help
+ This option instructions the compiler to generate Thumb2
+ instructions, which allows to mix 16 bits instructions and
+ 32 bits instructions. This generally provides a much smaller
+ compiled binary size.
+
endchoice
config BR2_ARCH
- default "arm" if BR2_arm
- default "armeb" if BR2_armeb
+ default "arm" if BR2_arm
+ default "armeb" if BR2_armeb
+ default "aarch64" if BR2_aarch64
+ default "aarch64_be" if BR2_aarch64_be
config BR2_ENDIAN
- default "LITTLE" if BR2_arm
- default "BIG" if BR2_armeb
-
-config BR2_GCC_TARGET_TUNE
- default "arm7tdmi" if BR2_arm7tdmi
- default "arm7tdmi" if BR2_arm720t
- default "arm7tdmi" if BR2_arm740t
- default "arm920" if BR2_arm920
+ default "LITTLE" if (BR2_arm || BR2_aarch64)
+ default "BIG" if (BR2_armeb || BR2_aarch64_be)
+
+config BR2_GCC_TARGET_CPU
+ # armv4
default "arm920t" if BR2_arm920t
default "arm922t" if BR2_arm922t
+ default "fa526" if BR2_fa526
+ default "strongarm" if BR2_strongarm
+ # armv5
default "arm926ej-s" if BR2_arm926t
+ default "iwmmxt" if BR2_iwmmxt
+ default "xscale" if BR2_xscale
+ # armv6
default "arm1136j-s" if BR2_arm1136j_s
default "arm1136jf-s" if BR2_arm1136jf_s
default "arm1176jz-s" if BR2_arm1176jz_s
default "arm1176jzf-s" if BR2_arm1176jzf_s
+ default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2
+ default "mpcorenovfp" if BR2_arm11mpcore
+ # armv7a
default "cortex-a5" if BR2_cortex_a5
default "cortex-a7" if BR2_cortex_a7
default "cortex-a8" if BR2_cortex_a8
default "cortex-a9" if BR2_cortex_a9
+ default "cortex-a12" if BR2_cortex_a12
default "cortex-a15" if BR2_cortex_a15
- default "fa526" if BR2_fa526
+ default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7
+ default "cortex-a17" if BR2_cortex_a17
+ default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7
default "marvell-pj4" if BR2_pj4
- default "strongarm" if BR2_strongarm
- default "xscale" if BR2_xscale
- default "iwmmxt" if BR2_iwmmxt
-
-config BR2_GCC_TARGET_ARCH
- default "armv4t" if BR2_arm7tdmi
- default "armv4t" if BR2_arm720t
- default "armv4t" if BR2_arm920t
- default "armv4t" if BR2_arm922t
- default "armv5te" if BR2_arm926t
- default "armv5t" if BR2_arm10t
- default "armv6j" if BR2_arm1136jf_s_r0
- default "armv6k" if BR2_arm1136jf_s_r1
- default "armv6zk" if BR2_arm1176jz_s
- default "armv6zk" if BR2_arm1176jzf_s
- default "armv7-a" if BR2_cortex_a5
- default "armv7-a" if BR2_cortex_a7
- default "armv7-a" if BR2_cortex_a8
- default "armv7-a" if BR2_cortex_a9
- default "armv7-a" if BR2_cortex_a15
- default "armv4" if BR2_fa526
- default "armv7-a" if BR2_pj4
- default "armv4" if BR2_strongarm
- default "armv5te" if BR2_xscale
- default "iwmmxt" if BR2_iwmmxt
+ # armv7m
+ default "cortex-m3" if BR2_cortex_m3
+ default "cortex-m4" if BR2_cortex_m4
+ # armv8a
+ default "cortex-a32" if BR2_cortex_a32
+ default "cortex-a35" if BR2_cortex_a35
+ default "cortex-a53" if BR2_cortex_a53
+ default "cortex-a57" if BR2_cortex_a57
+ default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53
+ default "cortex-a72" if BR2_cortex_a72
+ default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53
+ default "cortex-a73" if BR2_cortex_a73
+ default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35
+ default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53
+ default "exynos-m1" if BR2_exynos_m1
+ default "falkor" if BR2_falkor
+ default "qdf24xx" if BR2_qdf24xx
+ default "thunderx" if BR2_thunderx
+ default "thunderxt81" if BR2_thunderxt81
+ default "thunderxt83" if BR2_thunderxt83
+ default "thunderxt88" if BR2_thunderxt88
+ default "thunderxt88p1" if BR2_thunderxt88p1
+ default "xgene1" if BR2_xgene1
+ # armv8.1a
+ default "thunderx2t99" if BR2_thunderx2t99
+ default "thunderx2t99p1" if BR2_thunderx2t99p1
+ default "vulcan" if BR2_vulcan
config BR2_GCC_TARGET_ABI
- default "aapcs-linux"
+ default "aapcs-linux" if BR2_arm || BR2_armeb
+ default "lp64" if BR2_aarch64 || BR2_aarch64_be
config BR2_GCC_TARGET_FPU
default "vfp" if BR2_ARM_FPU_VFPV2
default "vfpv3" if BR2_ARM_FPU_VFPV3
- default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
- default "vfpv4" if BR2_ARM_FPU_VFPV4
- default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
- default "neon" if BR2_ARM_FPU_NEON
- default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
+ default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16
+ default "vfpv4" if BR2_ARM_FPU_VFPV4
+ default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
+ default "neon" if BR2_ARM_FPU_NEON
+ default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
+ default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
+ default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
+ depends on BR2_arm || BR2_armeb
config BR2_GCC_TARGET_FLOAT_ABI
default "soft" if BR2_ARM_SOFT_FLOAT
default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI
default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF
+
+config BR2_GCC_TARGET_MODE
+ default "arm" if BR2_ARM_INSTRUCTIONS_ARM
+ default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2
+
+config BR2_READELF_ARCH_NAME
+ default "ARM" if BR2_arm || BR2_armeb
+ default "AArch64" if BR2_aarch64 || BR2_aarch64_be
projects / coffee / buildroot.git / blobdiff