arm/tegra: prepare clock code for multiple tegra variants

[can-eth-gw-linux.git] / arch / arm / mach-tegra / clock.c

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f8d41ffc0ca984a5685f8ed5975b27c8c513e5c1..a8f359d8ae174f1bec4e7bb0a9f3ea61e708dc30 100644 (file)
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -387,13 +387,15 @@ EXPORT_SYMBOL(tegra_clk_init_from_table);
 
 void tegra_periph_reset_deassert(struct clk *c)
 {
-       tegra2_periph_reset_deassert(c);
+       BUG_ON(!c->ops->reset);
+       c->ops->reset(c, false);
 }
 EXPORT_SYMBOL(tegra_periph_reset_deassert);
 
 void tegra_periph_reset_assert(struct clk *c)
 {
-       tegra2_periph_reset_assert(c);
+       BUG_ON(!c->ops->reset);
+       c->ops->reset(c, true);
 }
 EXPORT_SYMBOL(tegra_periph_reset_assert);
 
@@ -402,20 +404,6 @@ void __init tegra_init_clock(void)
        tegra2_init_clocks();
 }
 
-/*
- * The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB.
- */
-void tegra_sdmmc_tap_delay(struct clk *c, int delay)
-{
-       unsigned long flags;
-
-       spin_lock_irqsave(&c->spinlock, flags);
-       tegra2_sdmmc_tap_delay(c, delay);
-       spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
 #ifdef CONFIG_DEBUG_FS
 
 static int __clk_lock_all_spinlocks(void)