Merge branch 'omap/headers4' into next/dt

[can-eth-gw-linux.git] / arch / arm / mach-omap2 / pm34xx.c

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4c85762107bdefc57b08907f92a6df1e0391fbc2..11f9669eb7ede4becc1aab56173f0927a17c9e03 100644 (file)
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -653,14 +653,17 @@ static void __init pm_errata_configure(void)
                /* Enable the l2 cache toggling in sleep logic */
                enable_omap3630_toggle_l2_on_restore();
                if (omap_rev() < OMAP3630_REV_ES1_2)
-                       pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
+                       pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
+                                         PM_PER_MEMORIES_ERRATUM_i582);
+       } else if (cpu_is_omap34xx()) {
+               pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
        }
 }
 
 int __init omap3_pm_init(void)
 {
        struct power_state *pwrst, *tmp;
-       struct clockdomain *neon_clkdm, *mpu_clkdm;
+       struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
        int ret;
 
        if (!omap3_has_io_chain_ctrl())
@@ -712,6 +715,8 @@ int __init omap3_pm_init(void)
 
        neon_clkdm = clkdm_lookup("neon_clkdm");
        mpu_clkdm = clkdm_lookup("mpu_clkdm");
+       per_clkdm = clkdm_lookup("per_clkdm");
+       wkup_clkdm = clkdm_lookup("wkup_clkdm");
 
 #ifdef CONFIG_SUSPEND
        omap_pm_suspend = omap3_pm_suspend;
@@ -728,6 +733,27 @@ int __init omap3_pm_init(void)
        if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
                omap3630_ctrl_disable_rta();
 
+       /*
+        * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
+        * not correctly reset when the PER powerdomain comes back
+        * from OFF or OSWR when the CORE powerdomain is kept active.
+        * See OMAP36xx Erratum i582 "PER Domain reset issue after
+        * Domain-OFF/OSWR Wakeup".  This wakeup dependency is not a
+        * complete workaround.  The kernel must also prevent the PER
+        * powerdomain from going to OSWR/OFF while the CORE
+        * powerdomain is not going to OSWR/OFF.  And if PER last
+        * power state was off while CORE last power state was ON, the
+        * UART3/4 and McBSP2/3 SIDETONE devices need to run a
+        * self-test using their loopback tests; if that fails, those
+        * devices are unusable until the PER/CORE can complete a transition
+        * from ON to OSWR/OFF and then back to ON.
+        *
+        * XXX Technically this workaround is only needed if off-mode
+        * or OSWR is enabled.
+        */
+       if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
+               clkdm_add_wkdep(per_clkdm, wkup_clkdm);
+
        clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
        if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
                omap3_secure_ram_storage =