]> rtime.felk.cvut.cz Git - can-eth-gw-linux.git/blobdiff - arch/arm/boot/dts/imx6q.dtsi
ARM i.MX dtsi: Add default bus-width property for esdhc controller
[can-eth-gw-linux.git] / arch / arm / boot / dts / imx6q.dtsi
index 35e5895ba3df31856c73193a6bf79f791d54f985..663fb869eb20af0963bc0e7fce58a189f59104e9 100644 (file)
                                #clock-cells = <1>;
                        };
 
-                       anatop@020c8000 {
-                               compatible = "fsl,imx6q-anatop";
+                       anatop: anatop@020c8000 {
+                               compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
                                reg = <0x020c8000 0x1000>;
                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
 
                                interrupts = <0 89 0x04 0 90 0x04>;
                        };
 
+                       gpr: iomuxc-gpr@020e0000 {
+                               compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+                               reg = <0x020e0000 0x38>;
+                       };
+
                        iomuxc@020e0000 {
                                compatible = "fsl,imx6q-iomuxc";
                                reg = <0x020e0000 0x4000>;
                                interrupts = <0 22 0x04>;
                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
                                clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
                                status = "disabled";
                        };
 
                                interrupts = <0 23 0x04>;
                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
                                clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
                                status = "disabled";
                        };
 
                                interrupts = <0 24 0x04>;
                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
                                clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
                                status = "disabled";
                        };
 
                                interrupts = <0 25 0x04>;
                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
                                clock-names = "ipg", "ahb", "per";
+                               bus-width = <4>;
                                status = "disabled";
                        };
 
                        i2c@021a0000 { /* I2C1 */
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a0000 0x4000>;
                                interrupts = <0 36 0x04>;
                                clocks = <&clks 125>;
                        i2c@021a4000 { /* I2C2 */
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a4000 0x4000>;
                                interrupts = <0 37 0x04>;
                                clocks = <&clks 126>;
                        i2c@021a8000 { /* I2C3 */
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
+                               compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021a8000 0x4000>;
                                interrupts = <0 38 0x04>;
                                clocks = <&clks 127>;