ARM: tegra: Add AUXDATA for Tegra20 host1x

[can-eth-gw-linux.git] / arch / arm / mach-tegra / board-dt-tegra20.c

diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index aa5325cd1c4289ab16d9a6566ac4ee8c740bbc24..734d9cc87f2e4ef0daf7b66be2ce5995585bd585 100644 (file)
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -40,12 +40,10 @@
 #include <asm/mach/time.h>
 #include <asm/setup.h>
 
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-
 #include "board.h"
 #include "clock.h"
 #include "common.h"
+#include "iomap.h"
 
 struct tegra_ehci_platform_data tegra_ehci1_pdata = {
        .operating_mode = TEGRA_USB_OTG,
@@ -91,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
                       &tegra_ehci3_pdata),
        OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
        OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
+       OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
        {}
 };
 
@@ -104,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
        { "pll_a",      "pll_p_out1",   56448000,       true },
        { "pll_a_out0", "pll_a",        11289600,       true },
        { "cdev1",      NULL,           0,              true },
+       { "blink",      "clk_32k",      32768,          true },
        { "i2s1",       "pll_a_out0",   11289600,       false},
        { "i2s2",       "pll_a_out0",   11289600,       false},
+       { "sdmmc1",     "pll_p",        48000000,       false},
+       { "sdmmc3",     "pll_p",        48000000,       false},
+       { "sdmmc4",     "pll_p",        48000000,       false},
+       { "spi",        "pll_p",        20000000,       false },
+       { "sbc1",       "pll_p",        100000000,      false },
+       { "sbc2",       "pll_p",        100000000,      false },
+       { "sbc3",       "pll_p",        100000000,      false },
+       { "sbc4",       "pll_p",        100000000,      false },
+       { "host1x",     "pll_c",        150000000,      false },
+       { "disp1",      "pll_p",        600000000,      false },
+       { "disp2",      "pll_p",        600000000,      false },
        { NULL,         NULL,           0,              0},
 };