2 * SMS/SDRC (SDRAM controller) common code for OMAP2/3
4 * Copyright (C) 2005, 2008 Texas Instruments Inc.
5 * Copyright (C) 2005, 2008 Nokia Corporation
7 * Tony Lindgren <tony@atomide.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
26 #include "../plat-omap/sram.h"
32 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
34 void __iomem *omap2_sdrc_base;
35 void __iomem *omap2_sms_base;
37 struct omap2_sms_regs {
41 static struct omap2_sms_regs sms_context;
43 /* SDRC_POWER register bits */
44 #define SDRC_POWER_EXTCLKDIS_SHIFT 3
45 #define SDRC_POWER_PWDENA_SHIFT 2
46 #define SDRC_POWER_PAGEPOLICY_SHIFT 0
49 * omap2_sms_save_context - Save SMS registers
51 * Save SMS registers that need to be restored after off mode.
53 void omap2_sms_save_context(void)
55 sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
59 * omap2_sms_restore_context - Restore SMS registers
61 * Restore SMS registers that need to be Restored after off mode.
63 void omap2_sms_restore_context(void)
65 sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
69 * omap2_sdrc_get_params - return SDRC register values for a given clock rate
70 * @r: SDRC clock rate (in Hz)
71 * @sdrc_cs0: chip select 0 ram timings **
72 * @sdrc_cs1: chip select 1 ram timings **
74 * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
75 * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
76 * structs,for a given SDRC clock rate 'r'.
77 * These parameters control various timing delays in the SDRAM controller
78 * that are expressed in terms of the number of SDRC clock cycles to
79 * wait; hence the clock rate dependency.
81 * Supports 2 different timing parameters for both chip selects.
83 * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
84 * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
85 * as sdrc_init_params_cs_0.
87 * Fills in the struct omap_sdrc_params * for each chip select.
88 * Returns 0 upon success or -1 upon failure.
90 int omap2_sdrc_get_params(unsigned long r,
91 struct omap_sdrc_params **sdrc_cs0,
92 struct omap_sdrc_params **sdrc_cs1)
94 struct omap_sdrc_params *sp0, *sp1;
96 if (!sdrc_init_params_cs0)
99 sp0 = sdrc_init_params_cs0;
100 sp1 = sdrc_init_params_cs1;
102 while (sp0->rate && sp0->rate != r) {
104 if (sdrc_init_params_cs1)
117 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
119 if (omap2_globals->sdrc)
120 omap2_sdrc_base = omap2_globals->sdrc;
121 if (omap2_globals->sms)
122 omap2_sms_base = omap2_globals->sms;
126 * omap2_sdrc_init - initialize SMS, SDRC devices on boot
127 * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
128 * Support for 2 chip selects timings
130 * Turn on smart idle modes for SDRAM scheduler and controller.
131 * Program a known-good configuration for the SDRC to deal with buggy
134 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
135 struct omap_sdrc_params *sdrc_cs1)
139 l = sms_read_reg(SMS_SYSCONFIG);
142 sms_write_reg(l, SMS_SYSCONFIG);
144 l = sdrc_read_reg(SDRC_SYSCONFIG);
147 sdrc_write_reg(l, SDRC_SYSCONFIG);
149 sdrc_init_params_cs0 = sdrc_cs0;
150 sdrc_init_params_cs1 = sdrc_cs1;
152 /* XXX Enable SRFRONIDLEREQ here also? */
154 * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
155 * can cause random memory corruption
157 l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
158 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
159 sdrc_write_reg(l, SDRC_POWER);
160 omap2_sms_save_context();