drivers/staging/tm6000/tm6000-stds.c

   1 /*
   2  *  tm6000-stds.c - driver for TM5600/TM6000/TM6010 USB video capture devices
   3  *
   4  *  Copyright (C) 2007 Mauro Carvalho Chehab <mchehab@redhat.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation version 2
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include "tm6000.h"
  23 #include "tm6000-regs.h"
  24
  25 static unsigned int tm6010_a_mode = 0;
  26 module_param(tm6010_a_mode, int, 0644);
  27 MODULE_PARM_DESC(tm6010_a_mode, "set tm6010 sif audio mode");
  28
  29 struct tm6000_reg_settings {
  30         unsigned char req;
  31         unsigned char reg;
  32         unsigned char value;
  33 };
  34
  35
  36 struct tm6000_std_settings {
  37         v4l2_std_id id;
  38         struct tm6000_reg_settings common[27];
  39 };
  40
  41 static struct tm6000_std_settings composite_stds[] = {
  42         {
  43                 .id = V4L2_STD_PAL_M,
  44                 .common = {
  45                         {TM6010_REQ07_R3F_RESET, 0x01},
  46                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04},
  47                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
  48                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
  49                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
  50                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
  51                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
  52                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
  53                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
  54                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
  55                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
  56                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
  57                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
  58                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
  59                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
  60                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20},
  61                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
  62                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
  63                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
  64                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
  65                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
  66
  67                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
  68                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
  69                         {TM6010_REQ07_R3F_RESET, 0x00},
  70                         {0, 0, 0},
  71                 },
  72          }, {
  73                 .id = V4L2_STD_PAL_Nc,
  74                 .common = {
  75                         {TM6010_REQ07_R3F_RESET, 0x01},
  76                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36},
  77                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
  78                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
  79                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
  80                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
  81                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
  82                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
  83                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
  84                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
  85                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
  86                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
  87                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
  88                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
  89                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
  90                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
  91                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
  92                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
  93                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
  94                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
  95                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
  96
  97                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
  98                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
  99                         {TM6010_REQ07_R3F_RESET, 0x00},
 100                         {0, 0, 0},
 101                 },
 102         }, {
 103                 .id = V4L2_STD_PAL,
 104                 .common = {
 105                         {TM6010_REQ07_R3F_RESET, 0x01},
 106                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32},
 107                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 108                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 109                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
 110                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 111                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
 112                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
 113                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
 114                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
 115                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 116                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 117                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 118                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 119                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
 120                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
 121                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
 122                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
 123                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 124                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
 125                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 126
 127                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
 128                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 129                         {TM6010_REQ07_R3F_RESET, 0x00},
 130                         {0, 0, 0},
 131                 },
 132          }, {
 133                 .id = V4L2_STD_SECAM,
 134                 .common = {
 135                         {TM6010_REQ07_R3F_RESET, 0x01},
 136                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
 137                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 138                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 139                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
 140                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 141                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
 142                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
 143                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
 144                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
 145                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 146                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 147                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 148                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 149                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
 150                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
 151                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
 152                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
 153                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
 154                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
 155                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
 156
 157                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 158                         {TM6010_REQ07_R3F_RESET, 0x00},
 159                         {0, 0, 0},
 160                 },
 161         }, {
 162                 .id = V4L2_STD_NTSC,
 163                 .common = {
 164                         {TM6010_REQ07_R3F_RESET, 0x01},
 165                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00},
 166                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
 167                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 168                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
 169                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 170                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
 171                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
 172                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
 173                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
 174                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 175                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 176                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 177                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 178                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
 179                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
 180                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
 181                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
 182                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 183                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
 184                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 185
 186                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
 187                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 188                         {TM6010_REQ07_R3F_RESET, 0x00},
 189                         {0, 0, 0},
 190                 },
 191         },
 192 };
 193
 194 static struct tm6000_std_settings svideo_stds[] = {
 195         {
 196                 .id = V4L2_STD_PAL_M,
 197                 .common = {
 198                         {TM6010_REQ07_R3F_RESET, 0x01},
 199                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05},
 200                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 201                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 202                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
 203                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 204                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
 205                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
 206                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
 207                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
 208                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 209                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 210                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 211                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 212                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
 213                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
 214                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
 215                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
 216                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 217                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
 218                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 219
 220                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
 221                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 222                         {TM6010_REQ07_R3F_RESET, 0x00},
 223                         {0, 0, 0},
 224                 },
 225         }, {
 226                 .id = V4L2_STD_PAL_Nc,
 227                 .common = {
 228                         {TM6010_REQ07_R3F_RESET, 0x01},
 229                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37},
 230                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 231                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 232                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
 233                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 234                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
 235                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
 236                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
 237                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
 238                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 239                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 240                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 241                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 242                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
 243                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
 244                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
 245                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
 246                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 247                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
 248                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 249
 250                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
 251                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 252                         {TM6010_REQ07_R3F_RESET, 0x00},
 253                         {0, 0, 0},
 254                 },
 255         }, {
 256                 .id = V4L2_STD_PAL,
 257                 .common = {
 258                         {TM6010_REQ07_R3F_RESET, 0x01},
 259                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33},
 260                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 261                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 262                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04},
 263                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30},
 264                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
 265                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
 266                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
 267                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
 268                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 269                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 270                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 271                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 272                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
 273                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a},
 274                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
 275                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
 276                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 277                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
 278                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 279
 280                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
 281                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 282                         {TM6010_REQ07_R3F_RESET, 0x00},
 283                         {0, 0, 0},
 284                 },
 285          }, {
 286                 .id = V4L2_STD_SECAM,
 287                 .common = {
 288                         {TM6010_REQ07_R3F_RESET, 0x01},
 289                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39},
 290                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
 291                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 292                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03},
 293                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
 294                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
 295                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
 296                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
 297                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
 298                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 299                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 300                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 301                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 302                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
 303                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a},
 304                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
 305                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
 306                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
 307                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
 308                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
 309
 310                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 311                         {TM6010_REQ07_R3F_RESET, 0x00},
 312                         {0, 0, 0},
 313                 },
 314         }, {
 315                 .id = V4L2_STD_NTSC,
 316                 .common = {
 317                         {TM6010_REQ07_R3F_RESET, 0x01},
 318                         {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01},
 319                         {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
 320                         {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
 321                         {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03},
 322                         {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x30},
 323                         {TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b},
 324                         {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
 325                         {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
 326                         {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
 327                         {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
 328                         {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
 329                         {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
 330                         {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
 331                         {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
 332                         {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
 333                         {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
 334                         {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
 335                         {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
 336                         {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
 337                         {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
 338                         {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
 339
 340                         {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
 341                         {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
 342                         {TM6010_REQ07_R3F_RESET, 0x00},
 343                         {0, 0, 0},
 344                 },
 345         },
 346 };
 347
 348
 349 static int tm6000_set_audio_std(struct tm6000_core *dev)
 350 {
 351         uint8_t areg_02 = 0x04; /* GC1 Fixed gain 0dB */
 352         uint8_t areg_05 = 0x01; /* Auto 4.5 = M Japan, Auto 6.5 = DK */
 353         uint8_t areg_06 = 0x02; /* Auto de-emphasis, mannual channel mode */
 354         uint8_t nicam_flag = 0; /* No NICAM */
 355
 356         if (dev->radio) {
 357                 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
 358                 tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, 0x04);
 359                 tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
 360                 tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80);
 361                 tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x0c);
 362                 /* set mono or stereo */
 363                 if (dev->amode == V4L2_TUNER_MODE_MONO)
 364                         tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
 365                 else if (dev->amode == V4L2_TUNER_MODE_STEREO)
 366                         tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x02);
 367                 tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x18);
 368                 tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a);
 369                 tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x40);
 370                 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
 371                 tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
 372                 tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
 373                 return 0;
 374         }
 375
 376         switch (tm6010_a_mode) {
 377         /* auto */
 378         case 0:
 379                 switch (dev->norm) {
 380                 case V4L2_STD_NTSC_M_KR:
 381                         areg_05 |= 0x00;
 382                         break;
 383                 case V4L2_STD_NTSC_M_JP:
 384                         areg_05 |= 0x40;
 385                         break;
 386                 case V4L2_STD_NTSC_M:
 387                 case V4L2_STD_PAL_M:
 388                 case V4L2_STD_PAL_N:
 389                         areg_05 |= 0x20;
 390                         break;
 391                 case V4L2_STD_PAL_Nc:
 392                         areg_05 |= 0x60;
 393                         break;
 394                 case V4L2_STD_SECAM_L:
 395                         areg_05 |= 0x00;
 396                         break;
 397                 case V4L2_STD_DK:
 398                         areg_05 |= 0x10;
 399                         break;
 400                 }
 401                 break;
 402         /* A2 */
 403         case 1:
 404                 switch (dev->norm) {
 405                 case V4L2_STD_B:
 406                 case V4L2_STD_GH:
 407                         areg_05 = 0x05;
 408                         break;
 409                 case V4L2_STD_DK:
 410                         areg_05 = 0x09;
 411                         break;
 412                 }
 413                 break;
 414         /* NICAM */
 415         case 2:
 416                 switch (dev->norm) {
 417                 case V4L2_STD_B:
 418                 case V4L2_STD_GH:
 419                         areg_05 = 0x07;
 420                         break;
 421                 case V4L2_STD_DK:
 422                         areg_05 = 0x06;
 423                         break;
 424                 case V4L2_STD_PAL_I:
 425                         areg_05 = 0x08;
 426                         break;
 427                 case V4L2_STD_SECAM_L:
 428                         areg_05 = 0x0a;
 429                         areg_02 = 0x02;
 430                         break;
 431                 }
 432                 nicam_flag = 1;
 433                 break;
 434         /* other */
 435         case 3:
 436                 switch (dev->norm) {
 437                 /* DK3_A2 */
 438                 case V4L2_STD_DK:
 439                         areg_05 = 0x0b;
 440                         break;
 441                 /* Korea */
 442                 case V4L2_STD_NTSC_M_KR:
 443                         areg_05 = 0x04;
 444                         break;
 445                 /* EIAJ */
 446                 case V4L2_STD_NTSC_M_JP:
 447                         areg_05 = 0x03;
 448                         break;
 449                 default:
 450                         areg_05 = 0x02;
 451                         break;
 452                 }
 453                 break;
 454         }
 455
 456         tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
 457         tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, areg_02);
 458         tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
 459         tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0xa0);
 460         tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, areg_05);
 461         tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, areg_06);
 462         tm6000_set_reg(dev, TM6010_REQ08_R07_A_LEFT_VOL, 0x00);
 463         tm6000_set_reg(dev, TM6010_REQ08_R08_A_RIGHT_VOL, 0x00);
 464         tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x08);
 465         tm6000_set_reg(dev, TM6010_REQ08_R0A_A_I2S_MOD, 0x91);
 466         tm6000_set_reg(dev, TM6010_REQ08_R0B_A_ASD_THRES1, 0x20);
 467         tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x12);
 468         tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x20);
 469         tm6000_set_reg(dev, TM6010_REQ08_R0E_A_MONO_THRES1, 0xf0);
 470         tm6000_set_reg(dev, TM6010_REQ08_R0F_A_MONO_THRES2, 0x80);
 471         tm6000_set_reg(dev, TM6010_REQ08_R10_A_MUTE_THRES1, 0xc0);
 472         tm6000_set_reg(dev, TM6010_REQ08_R11_A_MUTE_THRES2, 0x80);
 473         tm6000_set_reg(dev, TM6010_REQ08_R12_A_AGC_U, 0x12);
 474         tm6000_set_reg(dev, TM6010_REQ08_R13_A_AGC_ERR_T, 0xfe);
 475         tm6000_set_reg(dev, TM6010_REQ08_R14_A_AGC_GAIN_INIT, 0x20);
 476         tm6000_set_reg(dev, TM6010_REQ08_R15_A_AGC_STEP_THR, 0x14);
 477         tm6000_set_reg(dev, TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe);
 478         tm6000_set_reg(dev, TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01);
 479         tm6000_set_reg(dev, TM6010_REQ08_R18_A_TR_CTRL, 0xa0);
 480         tm6000_set_reg(dev, TM6010_REQ08_R19_A_FH_2FH_GAIN, 0x32);
 481         tm6000_set_reg(dev, TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64);
 482         tm6000_set_reg(dev, TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20);
 483         tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1c, 0x00);
 484         tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0x1d, 0x00);
 485         tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
 486         tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
 487         tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
 488         tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
 489
 490         return 0;
 491 }
 492
 493 void tm6000_get_std_res(struct tm6000_core *dev)
 494 {
 495         /* Currently, those are the only supported resoltions */
 496         if (dev->norm & V4L2_STD_525_60)
 497                 dev->height = 480;
 498         else
 499                 dev->height = 576;
 500
 501         dev->width = 720;
 502 }
 503
 504 static int tm6000_load_std(struct tm6000_core *dev,
 505                            struct tm6000_reg_settings *set, int max_size)
 506 {
 507         int i, rc;
 508
 509         /* Load board's initialization table */
 510         for (i = 0; max_size; i++) {
 511                 if (!set[i].req)
 512                         return 0;
 513
 514                 rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value);
 515                 if (rc < 0) {
 516                         printk(KERN_ERR "Error %i while setting "
 517                                "req %d, reg %d to value %d\n",
 518                                rc, set[i].req, set[i].reg, set[i].value);
 519                         return rc;
 520                 }
 521         }
 522
 523         return 0;
 524 }
 525
 526 int tm6000_set_standard(struct tm6000_core *dev)
 527 {
 528         int i, rc = 0;
 529         u8 reg_07_fe = 0x8a;
 530         u8 reg_08_f1 = 0xfc;
 531         u8 reg_08_e2 = 0xf0;
 532         u8 reg_08_e6 = 0x0f;
 533
 534         tm6000_get_std_res(dev);
 535
 536         if (dev->radio) {
 537                 /* todo */
 538         }
 539
 540         if (dev->dev_type == TM6010) {
 541                 switch (dev->vinput[dev->input].vmux) {
 542                 case TM6000_VMUX_VIDEO_A:
 543                         tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4);
 544                         tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
 545                         tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
 546                         tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
 547                         tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
 548                         reg_07_fe |= 0x01;
 549                         break;
 550                 case TM6000_VMUX_VIDEO_B:
 551                         tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8);
 552                         tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
 553                         tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
 554                         tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
 555                         tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
 556                         reg_07_fe |= 0x01;
 557                         break;
 558                 case TM6000_VMUX_VIDEO_AB:
 559                         tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc);
 560                         tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8);
 561                         reg_08_e6 = 0x00;
 562                         tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2);
 563                         tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0);
 564                         tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
 565                         tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe0);
 566                         break;
 567                 default:
 568                         break;
 569                 }
 570                 switch (dev->vinput[dev->input].amux) {
 571                 case TM6000_AMUX_ADC1:
 572                         tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
 573                                 0x00, 0x0f);
 574                         break;
 575                 case TM6000_AMUX_ADC2:
 576                         tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
 577                                 0x08, 0x0f);
 578                         break;
 579                 case TM6000_AMUX_SIF1:
 580                         reg_08_e2 |= 0x02;
 581                         reg_08_e6 = 0x08;
 582                         reg_07_fe |= 0x40;
 583                         reg_08_f1 |= 0x02;
 584                         tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
 585                         tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
 586                                 0x02, 0x0f);
 587                         break;
 588                 case TM6000_AMUX_SIF2:
 589                         reg_08_e2 |= 0x02;
 590                         reg_08_e6 = 0x08;
 591                         reg_07_fe |= 0x40;
 592                         reg_08_f1 |= 0x02;
 593                         tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf7);
 594                         tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
 595                                 0x02, 0x0f);
 596                         break;
 597                 default:
 598                         break;
 599                 }
 600                 tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, reg_08_e2);
 601                 tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, reg_08_e6);
 602                 tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, reg_08_f1);
 603                 tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, reg_07_fe);
 604         } else {
 605                 switch (dev->vinput[dev->input].vmux) {
 606                 case TM6000_VMUX_VIDEO_A:
 607                         tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
 608                         tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
 609                         tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
 610                         tm6000_set_reg(dev,
 611                             REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 0);
 612                         break;
 613                 case TM6000_VMUX_VIDEO_B:
 614                         tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00);
 615                         tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
 616                         tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
 617                         tm6000_set_reg(dev,
 618                             REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 0);
 619                         break;
 620                 case TM6000_VMUX_VIDEO_AB:
 621                         tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
 622                         tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x10);
 623                         tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00);
 624                         tm6000_set_reg(dev,
 625                             REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 1);
 626                         break;
 627                 default:
 628                         break;
 629                 }
 630                 switch (dev->vinput[dev->input].amux) {
 631                 case TM6000_AMUX_ADC1:
 632                         tm6000_set_reg_mask(dev,
 633                                 TM6000_REQ07_REB_VADC_AADC_MODE, 0x00, 0x0f);
 634                         break;
 635                 case TM6000_AMUX_ADC2:
 636                         tm6000_set_reg_mask(dev,
 637                                 TM6000_REQ07_REB_VADC_AADC_MODE, 0x04, 0x0f);
 638                         break;
 639                 default:
 640                         break;
 641                 }
 642         }
 643         if (dev->vinput[dev->input].type == TM6000_INPUT_SVIDEO) {
 644                 for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) {
 645                         if (dev->norm & svideo_stds[i].id) {
 646                                 rc = tm6000_load_std(dev, svideo_stds[i].common,
 647                                                      sizeof(svideo_stds[i].
 648                                                             common));
 649                                 goto ret;
 650                         }
 651                 }
 652                 return -EINVAL;
 653         } else {
 654                 for (i = 0; i < ARRAY_SIZE(composite_stds); i++) {
 655                         if (dev->norm & composite_stds[i].id) {
 656                                 rc = tm6000_load_std(dev,
 657                                                      composite_stds[i].common,
 658                                                      sizeof(composite_stds[i].
 659                                                             common));
 660                                 goto ret;
 661                         }
 662                 }
 663                 return -EINVAL;
 664         }
 665
 666 ret:
 667         if (rc < 0)
 668                 return rc;
 669
 670         if ((dev->dev_type == TM6010) &&
 671             ((dev->vinput[dev->input].amux == TM6000_AMUX_SIF1) ||
 672             (dev->vinput[dev->input].amux == TM6000_AMUX_SIF2)))
 673                 tm6000_set_audio_std(dev);
 674
 675         msleep(40);
 676
 677
 678         return 0;
 679 }