arch/arm/mach-omap2/hsmmc.c

   1 /*
   2  * linux/arch/arm/mach-omap2/hsmmc.c
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Author: Texas Instruments
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/slab.h>
  14 #include <linux/string.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <mach/hardware.h>
  18 #include <linux/platform_data/gpio-omap.h>
  19
  20 #include <plat/mmc.h>
  21 #include <plat/omap-pm.h>
  22 #include <plat/mux.h>
  23 #include <plat/omap_device.h>
  24
  25 #include "mux.h"
  26 #include "hsmmc.h"
  27 #include "control.h"
  28
  29 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  30
  31 static u16 control_pbias_offset;
  32 static u16 control_devconf1_offset;
  33 static u16 control_mmc1;
  34
  35 #define HSMMC_NAME_LEN  9
  36
  37 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  38
  39 static int hsmmc_get_context_loss(struct device *dev)
  40 {
  41         return omap_pm_get_dev_context_loss_count(dev);
  42 }
  43
  44 #else
  45 #define hsmmc_get_context_loss NULL
  46 #endif
  47
  48 static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  49                                   int power_on, int vdd)
  50 {
  51         u32 reg, prog_io;
  52         struct omap_mmc_platform_data *mmc = dev->platform_data;
  53
  54         if (mmc->slots[0].remux)
  55                 mmc->slots[0].remux(dev, slot, power_on);
  56
  57         /*
  58          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  59          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
  60          * 1.8V and 3.0V modes, controlled by the PBIAS register.
  61          *
  62          * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  63          * is most naturally TWL VSIM; those pins also use PBIAS.
  64          *
  65          * FIXME handle VMMC1A as needed ...
  66          */
  67         if (power_on) {
  68                 if (cpu_is_omap2430()) {
  69                         reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  70                         if ((1 << vdd) >= MMC_VDD_30_31)
  71                                 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  72                         else
  73                                 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  74                         omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  75                 }
  76
  77                 if (mmc->slots[0].internal_clock) {
  78                         reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  79                         reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  80                         omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  81                 }
  82
  83                 reg = omap_ctrl_readl(control_pbias_offset);
  84                 if (cpu_is_omap3630()) {
  85                         /* Set MMC I/O to 52Mhz */
  86                         prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  87                         prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  88                         omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  89                 } else {
  90                         reg |= OMAP2_PBIASSPEEDCTRL0;
  91                 }
  92                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  93                 omap_ctrl_writel(reg, control_pbias_offset);
  94         } else {
  95                 reg = omap_ctrl_readl(control_pbias_offset);
  96                 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  97                 omap_ctrl_writel(reg, control_pbias_offset);
  98         }
  99 }
 100
 101 static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
 102                                  int power_on, int vdd)
 103 {
 104         u32 reg;
 105
 106         /* 100ms delay required for PBIAS configuration */
 107         msleep(100);
 108
 109         if (power_on) {
 110                 reg = omap_ctrl_readl(control_pbias_offset);
 111                 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
 112                 if ((1 << vdd) <= MMC_VDD_165_195)
 113                         reg &= ~OMAP2_PBIASLITEVMODE0;
 114                 else
 115                         reg |= OMAP2_PBIASLITEVMODE0;
 116                 omap_ctrl_writel(reg, control_pbias_offset);
 117         } else {
 118                 reg = omap_ctrl_readl(control_pbias_offset);
 119                 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
 120                         OMAP2_PBIASLITEVMODE0);
 121                 omap_ctrl_writel(reg, control_pbias_offset);
 122         }
 123 }
 124
 125 static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
 126                                   int power_on, int vdd)
 127 {
 128         u32 reg;
 129
 130         /*
 131          * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
 132          * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
 133          * 1.8V and 3.0V modes, controlled by the PBIAS register.
 134          */
 135         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 136         reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 137                 OMAP4_MMC1_PWRDNZ_MASK |
 138                 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
 139         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 140 }
 141
 142 static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
 143                                  int power_on, int vdd)
 144 {
 145         u32 reg;
 146         unsigned long timeout;
 147
 148         if (power_on) {
 149                 reg = omap4_ctrl_pad_readl(control_pbias_offset);
 150                 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
 151                 if ((1 << vdd) <= MMC_VDD_165_195)
 152                         reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 153                 else
 154                         reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
 155                 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
 156                         OMAP4_MMC1_PWRDNZ_MASK);
 157                 omap4_ctrl_pad_writel(reg, control_pbias_offset);
 158
 159                 timeout = jiffies + msecs_to_jiffies(5);
 160                 do {
 161                         reg = omap4_ctrl_pad_readl(control_pbias_offset);
 162                         if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
 163                                 break;
 164                         usleep_range(100, 200);
 165                 } while (!time_after(jiffies, timeout));
 166
 167                 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
 168                         pr_err("Pbias Voltage is not same as LDO\n");
 169                         /* Caution : On VMODE_ERROR Power Down MMC IO */
 170                         reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
 171                         omap4_ctrl_pad_writel(reg, control_pbias_offset);
 172                 }
 173         }
 174 }
 175
 176 static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
 177 {
 178         u32 reg;
 179
 180         reg = omap_ctrl_readl(control_devconf1_offset);
 181         if (mmc->slots[0].internal_clock)
 182                 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
 183         else
 184                 reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
 185         omap_ctrl_writel(reg, control_devconf1_offset);
 186 }
 187
 188 static void hsmmc2_before_set_reg(struct device *dev, int slot,
 189                                    int power_on, int vdd)
 190 {
 191         struct omap_mmc_platform_data *mmc = dev->platform_data;
 192
 193         if (mmc->slots[0].remux)
 194                 mmc->slots[0].remux(dev, slot, power_on);
 195
 196         if (power_on)
 197                 hsmmc2_select_input_clk_src(mmc);
 198 }
 199
 200 static int am35x_hsmmc2_set_power(struct device *dev, int slot,
 201                                   int power_on, int vdd)
 202 {
 203         struct omap_mmc_platform_data *mmc = dev->platform_data;
 204
 205         if (power_on)
 206                 hsmmc2_select_input_clk_src(mmc);
 207
 208         return 0;
 209 }
 210
 211 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 212                                                         int vdd)
 213 {
 214         return 0;
 215 }
 216
 217 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
 218                         int controller_nr)
 219 {
 220         if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
 221                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
 222                 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
 223                                         OMAP_PIN_INPUT_PULLUP);
 224         if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
 225                 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
 226                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
 227                                         OMAP_PIN_INPUT_PULLUP);
 228         if (cpu_is_omap34xx()) {
 229                 if (controller_nr == 0) {
 230                         omap_mux_init_signal("sdmmc1_clk",
 231                                 OMAP_PIN_INPUT_PULLUP);
 232                         omap_mux_init_signal("sdmmc1_cmd",
 233                                 OMAP_PIN_INPUT_PULLUP);
 234                         omap_mux_init_signal("sdmmc1_dat0",
 235                                 OMAP_PIN_INPUT_PULLUP);
 236                         if (mmc_controller->slots[0].caps &
 237                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 238                                 omap_mux_init_signal("sdmmc1_dat1",
 239                                         OMAP_PIN_INPUT_PULLUP);
 240                                 omap_mux_init_signal("sdmmc1_dat2",
 241                                         OMAP_PIN_INPUT_PULLUP);
 242                                 omap_mux_init_signal("sdmmc1_dat3",
 243                                         OMAP_PIN_INPUT_PULLUP);
 244                         }
 245                         if (mmc_controller->slots[0].caps &
 246                                                 MMC_CAP_8_BIT_DATA) {
 247                                 omap_mux_init_signal("sdmmc1_dat4",
 248                                         OMAP_PIN_INPUT_PULLUP);
 249                                 omap_mux_init_signal("sdmmc1_dat5",
 250                                         OMAP_PIN_INPUT_PULLUP);
 251                                 omap_mux_init_signal("sdmmc1_dat6",
 252                                         OMAP_PIN_INPUT_PULLUP);
 253                                 omap_mux_init_signal("sdmmc1_dat7",
 254                                         OMAP_PIN_INPUT_PULLUP);
 255                         }
 256                 }
 257                 if (controller_nr == 1) {
 258                         /* MMC2 */
 259                         omap_mux_init_signal("sdmmc2_clk",
 260                                 OMAP_PIN_INPUT_PULLUP);
 261                         omap_mux_init_signal("sdmmc2_cmd",
 262                                 OMAP_PIN_INPUT_PULLUP);
 263                         omap_mux_init_signal("sdmmc2_dat0",
 264                                 OMAP_PIN_INPUT_PULLUP);
 265
 266                         /*
 267                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7
 268                          * need to be muxed in the board-*.c files
 269                          */
 270                         if (mmc_controller->slots[0].caps &
 271                                 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
 272                                 omap_mux_init_signal("sdmmc2_dat1",
 273                                         OMAP_PIN_INPUT_PULLUP);
 274                                 omap_mux_init_signal("sdmmc2_dat2",
 275                                         OMAP_PIN_INPUT_PULLUP);
 276                                 omap_mux_init_signal("sdmmc2_dat3",
 277                                         OMAP_PIN_INPUT_PULLUP);
 278                         }
 279                         if (mmc_controller->slots[0].caps &
 280                                                         MMC_CAP_8_BIT_DATA) {
 281                                 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
 282                                         OMAP_PIN_INPUT_PULLUP);
 283                                 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
 284                                         OMAP_PIN_INPUT_PULLUP);
 285                                 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
 286                                         OMAP_PIN_INPUT_PULLUP);
 287                                 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
 288                                         OMAP_PIN_INPUT_PULLUP);
 289                         }
 290                 }
 291
 292                 /*
 293                  * For MMC3 the pins need to be muxed in the board-*.c files
 294                  */
 295         }
 296 }
 297
 298 static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
 299                                         struct omap_mmc_platform_data *mmc)
 300 {
 301         char *hc_name;
 302
 303         hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
 304         if (!hc_name) {
 305                 pr_err("Cannot allocate memory for controller slot name\n");
 306                 kfree(hc_name);
 307                 return -ENOMEM;
 308         }
 309
 310         if (c->name)
 311                 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
 312         else
 313                 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
 314                                                                 c->mmc, 1);
 315         mmc->slots[0].name = hc_name;
 316         mmc->nr_slots = 1;
 317         mmc->slots[0].caps = c->caps;
 318         mmc->slots[0].pm_caps = c->pm_caps;
 319         mmc->slots[0].internal_clock = !c->ext_clock;
 320         mmc->max_freq = c->max_freq;
 321         if (cpu_is_omap44xx())
 322                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
 323         else
 324                 mmc->reg_offset = 0;
 325
 326         mmc->get_context_loss_count = hsmmc_get_context_loss;
 327
 328         mmc->slots[0].switch_pin = c->gpio_cd;
 329         mmc->slots[0].gpio_wp = c->gpio_wp;
 330
 331         mmc->slots[0].remux = c->remux;
 332         mmc->slots[0].init_card = c->init_card;
 333
 334         if (c->cover_only)
 335                 mmc->slots[0].cover = 1;
 336
 337         if (c->nonremovable)
 338                 mmc->slots[0].nonremovable = 1;
 339
 340         if (c->power_saving)
 341                 mmc->slots[0].power_saving = 1;
 342
 343         if (c->no_off)
 344                 mmc->slots[0].no_off = 1;
 345
 346         if (c->no_off_init)
 347                 mmc->slots[0].no_regulator_off_init = c->no_off_init;
 348
 349         if (c->vcc_aux_disable_is_sleep)
 350                 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 351
 352         /*
 353          * NOTE:  MMC slots should have a Vcc regulator set up.
 354          * This may be from a TWL4030-family chip, another
 355          * controllable regulator, or a fixed supply.
 356          *
 357          * temporary HACK: ocr_mask instead of fixed supply
 358          */
 359         if (soc_is_am35xx())
 360                 mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
 361                                          MMC_VDD_26_27 |
 362                                          MMC_VDD_27_28 |
 363                                          MMC_VDD_29_30 |
 364                                          MMC_VDD_30_31 |
 365                                          MMC_VDD_31_32;
 366         else
 367                 mmc->slots[0].ocr_mask = c->ocr_mask;
 368
 369         if (!soc_is_am35xx())
 370                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 371
 372         if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
 373                 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
 374
 375         switch (c->mmc) {
 376         case 1:
 377                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 378                         /* on-chip level shifting via PBIAS0/PBIAS1 */
 379                         if (cpu_is_omap44xx()) {
 380                                 mmc->slots[0].before_set_reg =
 381                                                 omap4_hsmmc1_before_set_reg;
 382                                 mmc->slots[0].after_set_reg =
 383                                                 omap4_hsmmc1_after_set_reg;
 384                         } else {
 385                                 mmc->slots[0].before_set_reg =
 386                                                 omap_hsmmc1_before_set_reg;
 387                                 mmc->slots[0].after_set_reg =
 388                                                 omap_hsmmc1_after_set_reg;
 389                         }
 390                 }
 391
 392                 if (soc_is_am35xx())
 393                         mmc->slots[0].set_power = nop_mmc_set_power;
 394
 395                 /* OMAP3630 HSMMC1 supports only 4-bit */
 396                 if (cpu_is_omap3630() &&
 397                                 (c->caps & MMC_CAP_8_BIT_DATA)) {
 398                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 399                         c->caps |= MMC_CAP_4_BIT_DATA;
 400                         mmc->slots[0].caps = c->caps;
 401                 }
 402                 break;
 403         case 2:
 404                 if (soc_is_am35xx())
 405                         mmc->slots[0].set_power = am35x_hsmmc2_set_power;
 406
 407                 if (c->ext_clock)
 408                         c->transceiver = 1;
 409                 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
 410                         c->caps &= ~MMC_CAP_8_BIT_DATA;
 411                         c->caps |= MMC_CAP_4_BIT_DATA;
 412                 }
 413                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
 414                         /* off-chip level shifting, or none */
 415                         mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
 416                         mmc->slots[0].after_set_reg = NULL;
 417                 }
 418                 break;
 419         case 3:
 420         case 4:
 421         case 5:
 422                 mmc->slots[0].before_set_reg = NULL;
 423                 mmc->slots[0].after_set_reg = NULL;
 424                 break;
 425         default:
 426                 pr_err("MMC%d configuration not supported!\n", c->mmc);
 427                 kfree(hc_name);
 428                 return -ENODEV;
 429         }
 430         return 0;
 431 }
 432
 433 static int omap_hsmmc_done;
 434
 435 void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
 436 {
 437         struct platform_device *pdev;
 438         struct omap_mmc_platform_data *mmc_pdata;
 439         int res;
 440
 441         if (omap_hsmmc_done != 1)
 442                 return;
 443
 444         omap_hsmmc_done++;
 445
 446         for (; c->mmc; c++) {
 447                 if (!c->deferred)
 448                         continue;
 449
 450                 pdev = c->pdev;
 451                 if (!pdev)
 452                         continue;
 453
 454                 mmc_pdata = pdev->dev.platform_data;
 455                 if (!mmc_pdata)
 456                         continue;
 457
 458                 mmc_pdata->slots[0].switch_pin = c->gpio_cd;
 459                 mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
 460
 461                 res = omap_device_register(pdev);
 462                 if (res)
 463                         pr_err("Could not late init MMC %s\n",
 464                                c->name);
 465         }
 466 }
 467
 468 #define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
 469
 470 static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
 471                                         int ctrl_nr)
 472 {
 473         struct omap_hwmod *oh;
 474         struct omap_hwmod *ohs[1];
 475         struct omap_device *od;
 476         struct platform_device *pdev;
 477         char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
 478         struct omap_mmc_platform_data *mmc_data;
 479         struct omap_mmc_dev_attr *mmc_dev_attr;
 480         char *name;
 481         int res;
 482
 483         mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
 484         if (!mmc_data) {
 485                 pr_err("Cannot allocate memory for mmc device!\n");
 486                 return;
 487         }
 488
 489         res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
 490         if (res < 0)
 491                 goto free_mmc;
 492
 493         omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
 494
 495         name = "omap_hsmmc";
 496         res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
 497                      "mmc%d", ctrl_nr);
 498         WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
 499              "String buffer overflow in MMC%d device setup\n", ctrl_nr);
 500
 501         oh = omap_hwmod_lookup(oh_name);
 502         if (!oh) {
 503                 pr_err("Could not look up %s\n", oh_name);
 504                 goto free_name;
 505         }
 506         ohs[0] = oh;
 507         if (oh->dev_attr != NULL) {
 508                 mmc_dev_attr = oh->dev_attr;
 509                 mmc_data->controller_flags = mmc_dev_attr->flags;
 510                 /*
 511                  * erratum 2.1.1.128 doesn't apply if board has
 512                  * a transceiver is attached
 513                  */
 514                 if (hsmmcinfo->transceiver)
 515                         mmc_data->controller_flags &=
 516                                 ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
 517         }
 518
 519         pdev = platform_device_alloc(name, ctrl_nr - 1);
 520         if (!pdev) {
 521                 pr_err("Could not allocate pdev for %s\n", name);
 522                 goto free_name;
 523         }
 524         dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 525
 526         od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
 527         if (!od) {
 528                 pr_err("Could not allocate od for %s\n", name);
 529                 goto put_pdev;
 530         }
 531
 532         res = platform_device_add_data(pdev, mmc_data,
 533                               sizeof(struct omap_mmc_platform_data));
 534         if (res) {
 535                 pr_err("Could not add pdata for %s\n", name);
 536                 goto put_pdev;
 537         }
 538
 539         hsmmcinfo->pdev = pdev;
 540
 541         if (hsmmcinfo->deferred)
 542                 goto free_mmc;
 543
 544         res = omap_device_register(pdev);
 545         if (res) {
 546                 pr_err("Could not register od for %s\n", name);
 547                 goto free_od;
 548         }
 549
 550         goto free_mmc;
 551
 552 free_od:
 553         omap_device_delete(od);
 554
 555 put_pdev:
 556         platform_device_put(pdev);
 557
 558 free_name:
 559         kfree(mmc_data->slots[0].name);
 560
 561 free_mmc:
 562         kfree(mmc_data);
 563 }
 564
 565 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 566 {
 567         u32 reg;
 568
 569         if (omap_hsmmc_done)
 570                 return;
 571
 572         omap_hsmmc_done = 1;
 573
 574         if (!cpu_is_omap44xx()) {
 575                 if (cpu_is_omap2430()) {
 576                         control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
 577                         control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
 578                 } else {
 579                         control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
 580                         control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
 581                 }
 582         } else {
 583                 control_pbias_offset =
 584                         OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
 585                 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
 586                 reg = omap4_ctrl_pad_readl(control_mmc1);
 587                 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
 588                         OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
 589                 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
 590                         OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
 591                 reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
 592                         OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
 593                         OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
 594                 omap4_ctrl_pad_writel(reg, control_mmc1);
 595         }
 596
 597         for (; controllers->mmc; controllers++)
 598                 omap_hsmmc_init_one(controllers, controllers->mmc);
 599
 600 }
 601
 602 #endif