1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
23 #include <linux/kref.h>
26 #include "drm_global.h"
30 #include "psb_intel_drv.h"
36 /* Append new drm mode definition here, align with libdrm definition */
37 #define DRM_MODE_SCALE_NO_SCALE 2
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
43 CHIP_MFLD_0130 = 3, /* Medfield */
46 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
47 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
48 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
54 #define DRIVER_NAME "gma500"
55 #define DRIVER_DESC "DRM driver for the Intel GMA500"
57 #define PSB_DRM_DRIVER_DATE "2011-06-06"
58 #define PSB_DRM_DRIVER_MAJOR 1
59 #define PSB_DRM_DRIVER_MINOR 0
60 #define PSB_DRM_DRIVER_PATCHLEVEL 0
65 #define PSB_VDC_OFFSET 0x00000000
66 #define PSB_VDC_SIZE 0x000080000
67 #define MRST_MMIO_SIZE 0x0000C0000
68 #define MDFLD_MMIO_SIZE 0x000100000
69 #define PSB_SGX_SIZE 0x8000
70 #define PSB_SGX_OFFSET 0x00040000
71 #define MRST_SGX_OFFSET 0x00080000
73 * PCI resource identifiers
75 #define PSB_MMIO_RESOURCE 0
76 #define PSB_GATT_RESOURCE 2
77 #define PSB_GTT_RESOURCE 3
81 #define PSB_GMCH_CTRL 0x52
83 #define _PSB_GMCH_ENABLED 0x4
84 #define PSB_PGETBL_CTL 0x2020
85 #define _PSB_PGETBL_ENABLED 0x00000001
86 #define PSB_SGX_2D_SLAVE_PORT 0x4000
89 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
93 * SGX side MMU definitions (these can probably go)
97 * Flags for external memory type field.
99 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
100 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
101 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
105 #define PSB_PDE_MASK 0x003FFFFF
106 #define PSB_PDE_SHIFT 22
107 #define PSB_PTE_SHIFT 12
111 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
112 #define PSB_PTE_WO 0x0002 /* Write only */
113 #define PSB_PTE_RO 0x0004 /* Read only */
114 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
117 * VDC registers and bits
119 #define PSB_MSVDX_CLOCKGATING 0x2064
120 #define PSB_TOPAZ_CLOCKGATING 0x2068
121 #define PSB_HWSTAM 0x2098
122 #define PSB_INSTPM 0x20C0
123 #define PSB_INT_IDENTITY_R 0x20A4
124 #define _PSB_IRQ_ASLE (1<<0)
125 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
126 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
127 #define _PSB_DPST_PIPEB_FLAG (1<<4)
128 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
129 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
130 #define _PSB_DPST_PIPEA_FLAG (1<<6)
131 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
132 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
133 #define _MDFLD_MIPIA_FLAG (1<<16)
134 #define _MDFLD_MIPIC_FLAG (1<<17)
135 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
136 #define _PSB_IRQ_SGX_FLAG (1<<18)
137 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
138 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
140 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
141 _PSB_VSYNC_PIPEB_FLAG)
143 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
144 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
145 _MDFLD_PIPEB_EVENT_FLAG | \
146 _PSB_PIPEA_EVENT_FLAG | \
147 _PSB_VSYNC_PIPEA_FLAG | \
148 _MDFLD_MIPIA_FLAG | \
150 #define PSB_INT_IDENTITY_R 0x20A4
151 #define PSB_INT_MASK_R 0x20A8
152 #define PSB_INT_ENABLE_R 0x20A0
154 #define _PSB_MMU_ER_MASK 0x0001FF00
155 #define _PSB_MMU_ER_HOST (1 << 16)
164 #define GPIO_CLOCK_DIR_MASK (1 << 0)
165 #define GPIO_CLOCK_DIR_IN (0 << 1)
166 #define GPIO_CLOCK_DIR_OUT (1 << 1)
167 #define GPIO_CLOCK_VAL_MASK (1 << 2)
168 #define GPIO_CLOCK_VAL_OUT (1 << 3)
169 #define GPIO_CLOCK_VAL_IN (1 << 4)
170 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
171 #define GPIO_DATA_DIR_MASK (1 << 8)
172 #define GPIO_DATA_DIR_IN (0 << 9)
173 #define GPIO_DATA_DIR_OUT (1 << 9)
174 #define GPIO_DATA_VAL_MASK (1 << 10)
175 #define GPIO_DATA_VAL_OUT (1 << 11)
176 #define GPIO_DATA_VAL_IN (1 << 12)
177 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
179 #define VCLK_DIVISOR_VGA0 0x6000
180 #define VCLK_DIVISOR_VGA1 0x6004
181 #define VCLK_POST_DIV 0x6010
183 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
184 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
185 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
186 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
187 #define PSB_COMM_USER_IRQ (1024 >> 2)
188 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
189 #define PSB_COMM_FW (2048 >> 2)
191 #define PSB_UIRQ_VISTEST 1
192 #define PSB_UIRQ_OOM_REPLY 2
193 #define PSB_UIRQ_FIRE_TA_REPLY 3
194 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
196 #define PSB_2D_SIZE (256*1024*1024)
197 #define PSB_MAX_RELOC_PAGES 1024
199 #define PSB_LOW_REG_OFFS 0x0204
200 #define PSB_HIGH_REG_OFFS 0x0600
202 #define PSB_NUM_VBLANKS 2
205 #define PSB_2D_SIZE (256*1024*1024)
206 #define PSB_MAX_RELOC_PAGES 1024
208 #define PSB_LOW_REG_OFFS 0x0204
209 #define PSB_HIGH_REG_OFFS 0x0600
211 #define PSB_NUM_VBLANKS 2
212 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
213 #define PSB_LID_DELAY (DRM_HZ / 10)
215 #define MDFLD_PNW_B0 0x04
216 #define MDFLD_PNW_C0 0x08
218 #define MDFLD_DSR_2D_3D_0 (1 << 0)
219 #define MDFLD_DSR_2D_3D_2 (1 << 1)
220 #define MDFLD_DSR_CURSOR_0 (1 << 2)
221 #define MDFLD_DSR_CURSOR_2 (1 << 3)
222 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
223 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
224 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
225 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
226 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
227 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
229 #define MDFLD_DSR_RR 45
230 #define MDFLD_DPU_ENABLE (1 << 31)
231 #define MDFLD_DSR_FULLSCREEN (1 << 30)
232 #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
234 #define PSB_PWR_STATE_ON 1
235 #define PSB_PWR_STATE_OFF 2
237 #define PSB_PMPOLICY_NOPM 0
238 #define PSB_PMPOLICY_CLOCKGATING 1
239 #define PSB_PMPOLICY_POWERDOWN 2
241 #define PSB_PMSTATE_POWERUP 0
242 #define PSB_PMSTATE_CLOCKGATED 1
243 #define PSB_PMSTATE_POWERDOWN 2
244 #define PSB_PCIx_MSI_ADDR_LOC 0x94
245 #define PSB_PCIx_MSI_DATA_LOC 0x98
247 /* Medfield crystal settings */
248 #define KSEL_CRYSTAL_19 1
249 #define KSEL_BYPASS_19 5
250 #define KSEL_BYPASS_25 6
251 #define KSEL_BYPASS_83_100 7
253 struct opregion_header;
254 struct opregion_acpi;
255 struct opregion_swsci;
256 struct opregion_asle;
258 struct psb_intel_opregion {
259 struct opregion_header *header;
260 struct opregion_acpi *acpi;
261 struct opregion_swsci *swsci;
262 struct opregion_asle *asle;
264 u32 __iomem *lid_state;
267 struct sdvo_device_mapping {
278 struct i2c_adapter adapter;
279 struct i2c_adapter *force_bit;
284 * Register save state. This is used to hold the context when the
285 * device is powered off. In the case of Oaktrail this can (but does not
286 * yet) include screen blank. Operations occuring during the save
287 * update the register cache instead.
290 uint32_t saveDSPACNTR;
291 uint32_t saveDSPBCNTR;
292 uint32_t savePIPEACONF;
293 uint32_t savePIPEBCONF;
294 uint32_t savePIPEASRC;
295 uint32_t savePIPEBSRC;
299 uint32_t saveDPLL_A_MD;
300 uint32_t saveHTOTAL_A;
301 uint32_t saveHBLANK_A;
302 uint32_t saveHSYNC_A;
303 uint32_t saveVTOTAL_A;
304 uint32_t saveVBLANK_A;
305 uint32_t saveVSYNC_A;
306 uint32_t saveDSPASTRIDE;
307 uint32_t saveDSPASIZE;
308 uint32_t saveDSPAPOS;
309 uint32_t saveDSPABASE;
310 uint32_t saveDSPASURF;
311 uint32_t saveDSPASTATUS;
315 uint32_t saveDPLL_B_MD;
316 uint32_t saveHTOTAL_B;
317 uint32_t saveHBLANK_B;
318 uint32_t saveHSYNC_B;
319 uint32_t saveVTOTAL_B;
320 uint32_t saveVBLANK_B;
321 uint32_t saveVSYNC_B;
322 uint32_t saveDSPBSTRIDE;
323 uint32_t saveDSPBSIZE;
324 uint32_t saveDSPBPOS;
325 uint32_t saveDSPBBASE;
326 uint32_t saveDSPBSURF;
327 uint32_t saveDSPBSTATUS;
328 uint32_t saveVCLK_DIVISOR_VGA0;
329 uint32_t saveVCLK_DIVISOR_VGA1;
330 uint32_t saveVCLK_POST_DIV;
331 uint32_t saveVGACNTRL;
339 uint32_t savePP_CONTROL;
340 uint32_t savePP_CYCLE;
341 uint32_t savePFIT_CONTROL;
342 uint32_t savePaletteA[256];
343 uint32_t savePaletteB[256];
344 uint32_t saveCLOCKGATING;
346 uint32_t saveDSPATILEOFF;
347 uint32_t saveDSPBTILEOFF;
348 uint32_t saveDSPAADDR;
349 uint32_t saveDSPBADDR;
350 uint32_t savePFIT_AUTO_RATIOS;
351 uint32_t savePFIT_PGM_RATIOS;
352 uint32_t savePP_ON_DELAYS;
353 uint32_t savePP_OFF_DELAYS;
354 uint32_t savePP_DIVISOR;
355 uint32_t saveBCLRPAT_A;
356 uint32_t saveBCLRPAT_B;
357 uint32_t saveDSPALINOFF;
358 uint32_t saveDSPBLINOFF;
359 uint32_t savePERF_MODE;
366 uint32_t saveCHICKENBIT;
367 uint32_t saveDSPACURSOR_CTRL;
368 uint32_t saveDSPBCURSOR_CTRL;
369 uint32_t saveDSPACURSOR_BASE;
370 uint32_t saveDSPBCURSOR_BASE;
371 uint32_t saveDSPACURSOR_POS;
372 uint32_t saveDSPBCURSOR_POS;
373 uint32_t save_palette_a[256];
374 uint32_t save_palette_b[256];
375 uint32_t saveOV_OVADD;
376 uint32_t saveOV_OGAMC0;
377 uint32_t saveOV_OGAMC1;
378 uint32_t saveOV_OGAMC2;
379 uint32_t saveOV_OGAMC3;
380 uint32_t saveOV_OGAMC4;
381 uint32_t saveOV_OGAMC5;
382 uint32_t saveOVC_OVADD;
383 uint32_t saveOVC_OGAMC0;
384 uint32_t saveOVC_OGAMC1;
385 uint32_t saveOVC_OGAMC2;
386 uint32_t saveOVC_OGAMC3;
387 uint32_t saveOVC_OGAMC4;
388 uint32_t saveOVC_OGAMC5;
390 /* DPST register save */
391 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 uint32_t savePWM_CONTROL_LOGIC;
396 struct medfield_state {
399 uint32_t savePIPEACONF;
400 uint32_t saveHTOTAL_A;
401 uint32_t saveHBLANK_A;
402 uint32_t saveHSYNC_A;
403 uint32_t saveVTOTAL_A;
404 uint32_t saveVBLANK_A;
405 uint32_t saveVSYNC_A;
406 uint32_t savePIPEASRC;
407 uint32_t saveDSPASTRIDE;
408 uint32_t saveDSPALINOFF;
409 uint32_t saveDSPATILEOFF;
410 uint32_t saveDSPASIZE;
411 uint32_t saveDSPAPOS;
412 uint32_t saveDSPASURF;
413 uint32_t saveDSPACNTR;
414 uint32_t saveDSPASTATUS;
415 uint32_t save_palette_a[256];
420 uint32_t savePIPEBCONF;
421 uint32_t saveHTOTAL_B;
422 uint32_t saveHBLANK_B;
423 uint32_t saveHSYNC_B;
424 uint32_t saveVTOTAL_B;
425 uint32_t saveVBLANK_B;
426 uint32_t saveVSYNC_B;
427 uint32_t savePIPEBSRC;
428 uint32_t saveDSPBSTRIDE;
429 uint32_t saveDSPBLINOFF;
430 uint32_t saveDSPBTILEOFF;
431 uint32_t saveDSPBSIZE;
432 uint32_t saveDSPBPOS;
433 uint32_t saveDSPBSURF;
434 uint32_t saveDSPBCNTR;
435 uint32_t saveDSPBSTATUS;
436 uint32_t save_palette_b[256];
438 uint32_t savePIPECCONF;
439 uint32_t saveHTOTAL_C;
440 uint32_t saveHBLANK_C;
441 uint32_t saveHSYNC_C;
442 uint32_t saveVTOTAL_C;
443 uint32_t saveVBLANK_C;
444 uint32_t saveVSYNC_C;
445 uint32_t savePIPECSRC;
446 uint32_t saveDSPCSTRIDE;
447 uint32_t saveDSPCLINOFF;
448 uint32_t saveDSPCTILEOFF;
449 uint32_t saveDSPCSIZE;
450 uint32_t saveDSPCPOS;
451 uint32_t saveDSPCSURF;
452 uint32_t saveDSPCCNTR;
453 uint32_t saveDSPCSTATUS;
454 uint32_t save_palette_c[256];
457 uint32_t savePFIT_CONTROL;
458 uint32_t savePFIT_PGM_RATIOS;
459 uint32_t saveHDMIPHYMISCCTL;
460 uint32_t saveHDMIB_CONTROL;
464 uint32_t saveDSPCLK_GATE_D;
465 uint32_t saveRAMCLK_GATE_D;
467 uint32_t saveDSPFW[6];
469 uint32_t savePP_CONTROL;
470 uint32_t savePFIT_PGM_RATIOS;
472 uint32_t savePFIT_CONTROL;
473 uint32_t savePP_ON_DELAYS;
474 uint32_t savePP_OFF_DELAYS;
475 uint32_t savePP_CYCLE;
476 uint32_t saveVGACNTRL;
482 struct psb_save_area {
486 struct psb_state psb;
487 struct medfield_state mdfld;
488 struct cdv_state cdv;
490 uint32_t saveBLC_PWM_CTL2;
491 uint32_t saveBLC_PWM_CTL;
496 #define PSB_NUM_PIPE 3
498 struct drm_psb_private {
499 struct drm_device *dev;
500 const struct psb_ops *ops;
502 struct child_device_config *child_dev;
507 /* GTT Memory manager */
508 struct psb_gtt_mm *gtt_mm;
509 struct page *scratch_page;
510 u32 __iomem *gtt_map;
511 uint32_t stolen_base;
512 u8 __iomem *vram_addr;
513 unsigned long vram_stolen_size;
515 u16 gmch_ctrl; /* Saved GTT setup */
518 struct mutex gtt_mutex;
519 struct resource *gtt_mem; /* Our PCI resource */
521 struct psb_mmu_driver *mmu;
522 struct psb_mmu_pd *pf_pd;
528 uint8_t __iomem *sgx_reg;
529 uint8_t __iomem *vdc_reg;
530 uint32_t gatt_free_offset;
536 uint32_t vdc_irq_mask;
537 uint32_t pipestat[PSB_NUM_PIPE];
539 spinlock_t irqmask_lock;
552 struct psb_intel_mode_device mode_dev;
554 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
555 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
559 * OSPM info (Power management base) (can go ?)
568 u32 video_device_fuse;
570 /* PCI revision ID for B0:D2:F0 */
571 uint8_t platform_rev_id;
574 struct intel_gmbus *gmbus;
578 /* FIXME: The mappings should be parsed from bios but for now we can
579 pretend there are no mappings available */
580 struct sdvo_device_mapping sdvo_mappings[2];
581 u32 hotplug_supported_mask;
582 struct drm_property *broadcast_rgb_property;
583 struct drm_property *force_audio_property;
588 int backlight_duty_cycle; /* restore backlight to this value */
589 bool panel_wants_dither;
590 struct drm_display_mode *panel_fixed_mode;
591 struct drm_display_mode *lfp_lvds_vbt_mode;
592 struct drm_display_mode *sdvo_lvds_vbt_mode;
594 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
595 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
597 /* Feature bits from the VBIOS */
598 unsigned int int_tv_support:1;
599 unsigned int lvds_dither:1;
600 unsigned int lvds_vbt:1;
601 unsigned int int_crt_support:1;
602 unsigned int lvds_use_ssc:1;
606 u32 mipi_ctrl_display;
608 unsigned int core_freq;
609 uint32_t iLVDS_enable;
611 /* Runtime PM state */
615 struct oaktrail_vbt vbt_data;
616 struct oaktrail_gct_data gct_data;
618 /* Oaktrail HDMI state */
619 struct oaktrail_hdmi_dev *hdmi_priv;
625 struct psb_save_area regs;
635 struct work_struct hotplug_work;
641 struct timer_list lid_timer;
642 struct psb_intel_opregion opregion;
653 * Used for modifying backlight from
654 * xrandr -- consider removing and using HAL instead
656 struct backlight_device *backlight_device;
657 struct drm_property *backlight_property;
663 /* 2D acceleration */
670 int brightness_adjusted;
674 bool dpi_panel_on[3];
675 void *dsi_configs[2];
684 bool dplla_96mhz; /* DPLL data from the VBT */
689 * Operations for each board type
694 unsigned int accel_2d:1;
695 int pipes; /* Number of output pipes */
696 int crtcs; /* Number of CRTCs */
697 int sgx_offset; /* Base offset of SGX device */
698 int hdmi_mask; /* Mask of HDMI CRTCs */
699 int lvds_mask; /* Mask of LVDS CRTCs */
702 struct drm_crtc_helper_funcs const *crtc_helper;
703 struct drm_crtc_funcs const *crtc_funcs;
706 int (*chip_setup)(struct drm_device *dev);
707 void (*chip_teardown)(struct drm_device *dev);
708 /* Optional helper caller after modeset */
709 void (*errata)(struct drm_device *dev);
711 /* Display management hooks */
712 int (*output_init)(struct drm_device *dev);
713 int (*hotplug)(struct drm_device *dev);
714 void (*hotplug_enable)(struct drm_device *dev, bool on);
715 /* Power management hooks */
716 void (*init_pm)(struct drm_device *dev);
717 int (*save_regs)(struct drm_device *dev);
718 int (*restore_regs)(struct drm_device *dev);
719 int (*power_up)(struct drm_device *dev);
720 int (*power_down)(struct drm_device *dev);
722 void (*lvds_bl_power)(struct drm_device *dev, bool on);
723 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
725 int (*backlight_init)(struct drm_device *dev);
727 int i2c_bus; /* I2C bus identifier for Moorestown */
732 struct psb_mmu_driver;
734 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
735 extern int drm_pick_crtcs(struct drm_device *dev);
737 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
739 return (struct drm_psb_private *) dev->dev_private;
746 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
749 struct drm_psb_private *dev_priv);
750 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
751 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
753 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
754 uint32_t gtt_start, uint32_t gtt_pages);
755 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
758 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
759 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
760 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
761 unsigned long address,
763 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
765 unsigned long address,
766 uint32_t num_pages, int type);
767 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
771 * Enable / disable MMU for different requestors.
775 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
776 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
777 unsigned long address, uint32_t num_pages,
778 uint32_t desired_tile_stride,
779 uint32_t hw_tile_stride, int type);
780 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
781 unsigned long address, uint32_t num_pages,
782 uint32_t desired_tile_stride,
783 uint32_t hw_tile_stride);
788 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
789 extern int psb_irq_enable_dpst(struct drm_device *dev);
790 extern int psb_irq_disable_dpst(struct drm_device *dev);
791 extern void psb_irq_preinstall(struct drm_device *dev);
792 extern int psb_irq_postinstall(struct drm_device *dev);
793 extern void psb_irq_uninstall(struct drm_device *dev);
794 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
795 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
797 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
798 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
799 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
800 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
801 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
803 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
806 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
808 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
813 extern int gma_intel_opregion_init(struct drm_device *dev);
814 extern int gma_intel_opregion_exit(struct drm_device *dev);
819 extern int psbfb_probed(struct drm_device *dev);
820 extern int psbfb_remove(struct drm_device *dev,
821 struct drm_framebuffer *fb);
825 extern void psbfb_copyarea(struct fb_info *info,
826 const struct fb_copyarea *region);
827 extern int psbfb_sync(struct fb_info *info);
828 extern void psb_spank(struct drm_psb_private *dev_priv);
834 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
835 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
836 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
839 extern void psb_modeset_init(struct drm_device *dev);
840 extern void psb_modeset_cleanup(struct drm_device *dev);
841 extern int psb_fbdev_init(struct drm_device *dev);
844 int gma_backlight_init(struct drm_device *dev);
845 void gma_backlight_exit(struct drm_device *dev);
847 /* oaktrail_crtc.c */
848 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
850 /* oaktrail_lvds.c */
851 extern void oaktrail_lvds_init(struct drm_device *dev,
852 struct psb_intel_mode_device *mode_dev);
854 /* psb_intel_display.c */
855 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
856 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
858 /* psb_intel_lvds.c */
859 extern const struct drm_connector_helper_funcs
860 psb_intel_lvds_connector_helper_funcs;
861 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
864 extern int psb_gem_init_object(struct drm_gem_object *obj);
865 extern void psb_gem_free_object(struct drm_gem_object *obj);
866 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
867 struct drm_file *file);
868 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
869 struct drm_mode_create_dumb *args);
870 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
872 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
873 uint32_t handle, uint64_t *offset);
874 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
875 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
876 struct drm_file *file);
877 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
878 struct drm_file *file);
881 extern const struct psb_ops psb_chip_ops;
883 /* oaktrail_device.c */
884 extern const struct psb_ops oaktrail_chip_ops;
887 extern const struct psb_ops mdfld_chip_ops;
890 extern const struct psb_ops cdv_chip_ops;
893 * Debug print bits setting
895 #define PSB_D_GENERAL (1 << 0)
896 #define PSB_D_INIT (1 << 1)
897 #define PSB_D_IRQ (1 << 2)
898 #define PSB_D_ENTRY (1 << 3)
899 /* debug the get H/V BP/FP count */
900 #define PSB_D_HV (1 << 4)
901 #define PSB_D_DBI_BF (1 << 5)
902 #define PSB_D_PM (1 << 6)
903 #define PSB_D_RENDER (1 << 7)
904 #define PSB_D_REG (1 << 8)
905 #define PSB_D_MSVDX (1 << 9)
906 #define PSB_D_TOPAZ (1 << 10)
908 extern int drm_psb_no_fb;
909 extern int drm_idle_check_interval;
915 static inline u32 MRST_MSG_READ32(uint port, uint offset)
917 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
918 uint32_t ret_val = 0;
919 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
920 pci_write_config_dword(pci_root, 0xD0, mcr);
921 pci_read_config_dword(pci_root, 0xD4, &ret_val);
922 pci_dev_put(pci_root);
925 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
927 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
928 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
929 pci_write_config_dword(pci_root, 0xD4, value);
930 pci_write_config_dword(pci_root, 0xD0, mcr);
931 pci_dev_put(pci_root);
933 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
935 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
936 uint32_t ret_val = 0;
937 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
938 pci_write_config_dword(pci_root, 0xD0, mcr);
939 pci_read_config_dword(pci_root, 0xD4, &ret_val);
940 pci_dev_put(pci_root);
943 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
945 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
946 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
947 pci_write_config_dword(pci_root, 0xD4, value);
948 pci_write_config_dword(pci_root, 0xD0, mcr);
949 pci_dev_put(pci_root);
952 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
954 struct drm_psb_private *dev_priv = dev->dev_private;
955 return ioread32(dev_priv->vdc_reg + reg);
958 #define REG_READ(reg) REGISTER_READ(dev, (reg))
960 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
963 struct drm_psb_private *dev_priv = dev->dev_private;
964 iowrite32((val), dev_priv->vdc_reg + (reg));
967 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
969 static inline void REGISTER_WRITE16(struct drm_device *dev,
970 uint32_t reg, uint32_t val)
972 struct drm_psb_private *dev_priv = dev->dev_private;
973 iowrite16((val), dev_priv->vdc_reg + (reg));
976 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
978 static inline void REGISTER_WRITE8(struct drm_device *dev,
979 uint32_t reg, uint32_t val)
981 struct drm_psb_private *dev_priv = dev->dev_private;
982 iowrite8((val), dev_priv->vdc_reg + (reg));
985 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
987 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
988 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
990 /* #define TRAP_SGX_PM_FAULT 1 */
991 #ifdef TRAP_SGX_PM_FAULT
992 #define PSB_RSGX32(_offs) \
994 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
996 "access sgx when it's off!! (READ) %s, %d\n", \
997 __FILE__, __LINE__); \
1000 ioread32(dev_priv->sgx_reg + (_offs)); \
1003 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
1005 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
1007 #define MSVDX_REG_DUMP 0
1009 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1010 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))