arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24
  25 #include <plat/omap_hwmod.h>
  26 #include <plat/i2c.h>
  27 #include <plat/dma.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <linux/platform_data/asoc-ti-mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33 #include <plat/iommu.h>
  34
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "wd_timer.h"
  41
  42 /* Base offset for all OMAP4 interrupts external to MPUSS */
  43 #define OMAP44XX_IRQ_GIC_START  32
  44
  45 /* Base offset for all OMAP4 dma requests */
  46 #define OMAP44XX_DMA_REQ_START  1
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /*
  53  * 'c2c_target_fw' class
  54  * instance(s): c2c_target_fw
  55  */
  56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  57         .name   = "c2c_target_fw",
  58 };
  59
  60 /* c2c_target_fw */
  61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  62         .name           = "c2c_target_fw",
  63         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  64         .clkdm_name     = "d2d_clkdm",
  65         .prcm = {
  66                 .omap4 = {
  67                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  68                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  69                 },
  70         },
  71 };
  72
  73 /*
  74  * 'dmm' class
  75  * instance(s): dmm
  76  */
  77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  78         .name   = "dmm",
  79 };
  80
  81 /* dmm */
  82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  83         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  84         { .irq = -1 }
  85 };
  86
  87 static struct omap_hwmod omap44xx_dmm_hwmod = {
  88         .name           = "dmm",
  89         .class          = &omap44xx_dmm_hwmod_class,
  90         .clkdm_name     = "l3_emif_clkdm",
  91         .mpu_irqs       = omap44xx_dmm_irqs,
  92         .prcm = {
  93                 .omap4 = {
  94                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  95                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'emif_fw' class
 102  * instance(s): emif_fw
 103  */
 104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 105         .name   = "emif_fw",
 106 };
 107
 108 /* emif_fw */
 109 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 110         .name           = "emif_fw",
 111         .class          = &omap44xx_emif_fw_hwmod_class,
 112         .clkdm_name     = "l3_emif_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 116                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 117                 },
 118         },
 119 };
 120
 121 /*
 122  * 'l3' class
 123  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 124  */
 125 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 126         .name   = "l3",
 127 };
 128
 129 /* l3_instr */
 130 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 131         .name           = "l3_instr",
 132         .class          = &omap44xx_l3_hwmod_class,
 133         .clkdm_name     = "l3_instr_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 137                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 138                         .modulemode   = MODULEMODE_HWCTRL,
 139                 },
 140         },
 141 };
 142
 143 /* l3_main_1 */
 144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 145         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 146         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 147         { .irq = -1 }
 148 };
 149
 150 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 151         .name           = "l3_main_1",
 152         .class          = &omap44xx_l3_hwmod_class,
 153         .clkdm_name     = "l3_1_clkdm",
 154         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 158                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 159                 },
 160         },
 161 };
 162
 163 /* l3_main_2 */
 164 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 165         .name           = "l3_main_2",
 166         .class          = &omap44xx_l3_hwmod_class,
 167         .clkdm_name     = "l3_2_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 171                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /* l3_main_3 */
 177 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 178         .name           = "l3_main_3",
 179         .class          = &omap44xx_l3_hwmod_class,
 180         .clkdm_name     = "l3_instr_clkdm",
 181         .prcm = {
 182                 .omap4 = {
 183                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 184                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 185                         .modulemode   = MODULEMODE_HWCTRL,
 186                 },
 187         },
 188 };
 189
 190 /*
 191  * 'l4' class
 192  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 193  */
 194 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 195         .name   = "l4",
 196 };
 197
 198 /* l4_abe */
 199 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 200         .name           = "l4_abe",
 201         .class          = &omap44xx_l4_hwmod_class,
 202         .clkdm_name     = "abe_clkdm",
 203         .prcm = {
 204                 .omap4 = {
 205                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 206                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 207                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 208                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 209                 },
 210         },
 211 };
 212
 213 /* l4_cfg */
 214 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 215         .name           = "l4_cfg",
 216         .class          = &omap44xx_l4_hwmod_class,
 217         .clkdm_name     = "l4_cfg_clkdm",
 218         .prcm = {
 219                 .omap4 = {
 220                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 221                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 222                 },
 223         },
 224 };
 225
 226 /* l4_per */
 227 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 228         .name           = "l4_per",
 229         .class          = &omap44xx_l4_hwmod_class,
 230         .clkdm_name     = "l4_per_clkdm",
 231         .prcm = {
 232                 .omap4 = {
 233                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 234                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 235                 },
 236         },
 237 };
 238
 239 /* l4_wkup */
 240 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 241         .name           = "l4_wkup",
 242         .class          = &omap44xx_l4_hwmod_class,
 243         .clkdm_name     = "l4_wkup_clkdm",
 244         .prcm = {
 245                 .omap4 = {
 246                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 247                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 248                 },
 249         },
 250 };
 251
 252 /*
 253  * 'mpu_bus' class
 254  * instance(s): mpu_private
 255  */
 256 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 257         .name   = "mpu_bus",
 258 };
 259
 260 /* mpu_private */
 261 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 262         .name           = "mpu_private",
 263         .class          = &omap44xx_mpu_bus_hwmod_class,
 264         .clkdm_name     = "mpuss_clkdm",
 265         .prcm = {
 266                 .omap4 = {
 267                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 268                 },
 269         },
 270 };
 271
 272 /*
 273  * 'ocp_wp_noc' class
 274  * instance(s): ocp_wp_noc
 275  */
 276 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 277         .name   = "ocp_wp_noc",
 278 };
 279
 280 /* ocp_wp_noc */
 281 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 282         .name           = "ocp_wp_noc",
 283         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 284         .clkdm_name     = "l3_instr_clkdm",
 285         .prcm = {
 286                 .omap4 = {
 287                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 288                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 289                         .modulemode   = MODULEMODE_HWCTRL,
 290                 },
 291         },
 292 };
 293
 294 /*
 295  * Modules omap_hwmod structures
 296  *
 297  * The following IPs are excluded for the moment because:
 298  * - They do not need an explicit SW control using omap_hwmod API.
 299  * - They still need to be validated with the driver
 300  *   properly adapted to omap_hwmod / omap_device
 301  *
 302  * usim
 303  */
 304
 305 /*
 306  * 'aess' class
 307  * audio engine sub system
 308  */
 309
 310 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 311         .rev_offs       = 0x0000,
 312         .sysc_offs      = 0x0010,
 313         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 314         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 315                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 316                            MSTANDBY_SMART_WKUP),
 317         .sysc_fields    = &omap_hwmod_sysc_type2,
 318 };
 319
 320 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 321         .name   = "aess",
 322         .sysc   = &omap44xx_aess_sysc,
 323 };
 324
 325 /* aess */
 326 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 327         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 328         { .irq = -1 }
 329 };
 330
 331 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 332         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 333         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 334         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 340         { .dma_req = -1 }
 341 };
 342
 343 static struct omap_hwmod omap44xx_aess_hwmod = {
 344         .name           = "aess",
 345         .class          = &omap44xx_aess_hwmod_class,
 346         .clkdm_name     = "abe_clkdm",
 347         .mpu_irqs       = omap44xx_aess_irqs,
 348         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 349         .main_clk       = "aess_fck",
 350         .prcm = {
 351                 .omap4 = {
 352                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 353                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 354                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 355                         .modulemode   = MODULEMODE_SWCTRL,
 356                 },
 357         },
 358 };
 359
 360 /*
 361  * 'c2c' class
 362  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 363  * soc
 364  */
 365
 366 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 367         .name   = "c2c",
 368 };
 369
 370 /* c2c */
 371 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 372         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 373         { .irq = -1 }
 374 };
 375
 376 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 377         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 378         { .dma_req = -1 }
 379 };
 380
 381 static struct omap_hwmod omap44xx_c2c_hwmod = {
 382         .name           = "c2c",
 383         .class          = &omap44xx_c2c_hwmod_class,
 384         .clkdm_name     = "d2d_clkdm",
 385         .mpu_irqs       = omap44xx_c2c_irqs,
 386         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 387         .prcm = {
 388                 .omap4 = {
 389                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 390                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 391                 },
 392         },
 393 };
 394
 395 /*
 396  * 'counter' class
 397  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 398  */
 399
 400 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 401         .rev_offs       = 0x0000,
 402         .sysc_offs      = 0x0004,
 403         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 404         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 405         .sysc_fields    = &omap_hwmod_sysc_type1,
 406 };
 407
 408 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 409         .name   = "counter",
 410         .sysc   = &omap44xx_counter_sysc,
 411 };
 412
 413 /* counter_32k */
 414 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 415         .name           = "counter_32k",
 416         .class          = &omap44xx_counter_hwmod_class,
 417         .clkdm_name     = "l4_wkup_clkdm",
 418         .flags          = HWMOD_SWSUP_SIDLE,
 419         .main_clk       = "sys_32k_ck",
 420         .prcm = {
 421                 .omap4 = {
 422                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 423                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 424                 },
 425         },
 426 };
 427
 428 /*
 429  * 'ctrl_module' class
 430  * attila core control module + core pad control module + wkup pad control
 431  * module + attila wkup control module
 432  */
 433
 434 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 435         .rev_offs       = 0x0000,
 436         .sysc_offs      = 0x0010,
 437         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 438         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 439                            SIDLE_SMART_WKUP),
 440         .sysc_fields    = &omap_hwmod_sysc_type2,
 441 };
 442
 443 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 444         .name   = "ctrl_module",
 445         .sysc   = &omap44xx_ctrl_module_sysc,
 446 };
 447
 448 /* ctrl_module_core */
 449 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 450         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 451         { .irq = -1 }
 452 };
 453
 454 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 455         .name           = "ctrl_module_core",
 456         .class          = &omap44xx_ctrl_module_hwmod_class,
 457         .clkdm_name     = "l4_cfg_clkdm",
 458         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 459         .prcm = {
 460                 .omap4 = {
 461                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 462                 },
 463         },
 464 };
 465
 466 /* ctrl_module_pad_core */
 467 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 468         .name           = "ctrl_module_pad_core",
 469         .class          = &omap44xx_ctrl_module_hwmod_class,
 470         .clkdm_name     = "l4_cfg_clkdm",
 471         .prcm = {
 472                 .omap4 = {
 473                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 474                 },
 475         },
 476 };
 477
 478 /* ctrl_module_wkup */
 479 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 480         .name           = "ctrl_module_wkup",
 481         .class          = &omap44xx_ctrl_module_hwmod_class,
 482         .clkdm_name     = "l4_wkup_clkdm",
 483         .prcm = {
 484                 .omap4 = {
 485                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 486                 },
 487         },
 488 };
 489
 490 /* ctrl_module_pad_wkup */
 491 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 492         .name           = "ctrl_module_pad_wkup",
 493         .class          = &omap44xx_ctrl_module_hwmod_class,
 494         .clkdm_name     = "l4_wkup_clkdm",
 495         .prcm = {
 496                 .omap4 = {
 497                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 498                 },
 499         },
 500 };
 501
 502 /*
 503  * 'debugss' class
 504  * debug and emulation sub system
 505  */
 506
 507 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 508         .name   = "debugss",
 509 };
 510
 511 /* debugss */
 512 static struct omap_hwmod omap44xx_debugss_hwmod = {
 513         .name           = "debugss",
 514         .class          = &omap44xx_debugss_hwmod_class,
 515         .clkdm_name     = "emu_sys_clkdm",
 516         .main_clk       = "trace_clk_div_ck",
 517         .prcm = {
 518                 .omap4 = {
 519                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 520                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 521                 },
 522         },
 523 };
 524
 525 /*
 526  * 'dma' class
 527  * dma controller for data exchange between memory to memory (i.e. internal or
 528  * external memory) and gp peripherals to memory or memory to gp peripherals
 529  */
 530
 531 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 532         .rev_offs       = 0x0000,
 533         .sysc_offs      = 0x002c,
 534         .syss_offs      = 0x0028,
 535         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 536                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 537                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 538                            SYSS_HAS_RESET_STATUS),
 539         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 540                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 541         .sysc_fields    = &omap_hwmod_sysc_type1,
 542 };
 543
 544 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 545         .name   = "dma",
 546         .sysc   = &omap44xx_dma_sysc,
 547 };
 548
 549 /* dma dev_attr */
 550 static struct omap_dma_dev_attr dma_dev_attr = {
 551         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 552                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 553         .lch_count      = 32,
 554 };
 555
 556 /* dma_system */
 557 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 558         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 559         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 560         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 562         { .irq = -1 }
 563 };
 564
 565 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 566         .name           = "dma_system",
 567         .class          = &omap44xx_dma_hwmod_class,
 568         .clkdm_name     = "l3_dma_clkdm",
 569         .mpu_irqs       = omap44xx_dma_system_irqs,
 570         .main_clk       = "l3_div_ck",
 571         .prcm = {
 572                 .omap4 = {
 573                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 574                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 575                 },
 576         },
 577         .dev_attr       = &dma_dev_attr,
 578 };
 579
 580 /*
 581  * 'dmic' class
 582  * digital microphone controller
 583  */
 584
 585 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 586         .rev_offs       = 0x0000,
 587         .sysc_offs      = 0x0010,
 588         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 589                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 590         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 591                            SIDLE_SMART_WKUP),
 592         .sysc_fields    = &omap_hwmod_sysc_type2,
 593 };
 594
 595 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 596         .name   = "dmic",
 597         .sysc   = &omap44xx_dmic_sysc,
 598 };
 599
 600 /* dmic */
 601 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 602         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 603         { .irq = -1 }
 604 };
 605
 606 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 607         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 608         { .dma_req = -1 }
 609 };
 610
 611 static struct omap_hwmod omap44xx_dmic_hwmod = {
 612         .name           = "dmic",
 613         .class          = &omap44xx_dmic_hwmod_class,
 614         .clkdm_name     = "abe_clkdm",
 615         .mpu_irqs       = omap44xx_dmic_irqs,
 616         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 617         .main_clk       = "dmic_fck",
 618         .prcm = {
 619                 .omap4 = {
 620                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 621                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 622                         .modulemode   = MODULEMODE_SWCTRL,
 623                 },
 624         },
 625 };
 626
 627 /*
 628  * 'dsp' class
 629  * dsp sub-system
 630  */
 631
 632 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 633         .name   = "dsp",
 634 };
 635
 636 /* dsp */
 637 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 638         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 639         { .irq = -1 }
 640 };
 641
 642 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 643         { .name = "dsp", .rst_shift = 0 },
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .clkdm_name     = "tesla_clkdm",
 650         .mpu_irqs       = omap44xx_dsp_irqs,
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 657                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 658                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 659                         .modulemode   = MODULEMODE_HWCTRL,
 660                 },
 661         },
 662 };
 663
 664 /*
 665  * 'dss' class
 666  * display sub-system
 667  */
 668
 669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 670         .rev_offs       = 0x0000,
 671         .syss_offs      = 0x0014,
 672         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 673 };
 674
 675 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 676         .name   = "dss",
 677         .sysc   = &omap44xx_dss_sysc,
 678         .reset  = omap_dss_reset,
 679 };
 680
 681 /* dss */
 682 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 683         { .role = "sys_clk", .clk = "dss_sys_clk" },
 684         { .role = "tv_clk", .clk = "dss_tv_clk" },
 685         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 686 };
 687
 688 static struct omap_hwmod omap44xx_dss_hwmod = {
 689         .name           = "dss_core",
 690         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 691         .class          = &omap44xx_dss_hwmod_class,
 692         .clkdm_name     = "l3_dss_clkdm",
 693         .main_clk       = "dss_dss_clk",
 694         .prcm = {
 695                 .omap4 = {
 696                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 697                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 698                 },
 699         },
 700         .opt_clks       = dss_opt_clks,
 701         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 702 };
 703
 704 /*
 705  * 'dispc' class
 706  * display controller
 707  */
 708
 709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 710         .rev_offs       = 0x0000,
 711         .sysc_offs      = 0x0010,
 712         .syss_offs      = 0x0014,
 713         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 714                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 715                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 716                            SYSS_HAS_RESET_STATUS),
 717         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 718                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 719         .sysc_fields    = &omap_hwmod_sysc_type1,
 720 };
 721
 722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 723         .name   = "dispc",
 724         .sysc   = &omap44xx_dispc_sysc,
 725 };
 726
 727 /* dss_dispc */
 728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 729         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 730         { .irq = -1 }
 731 };
 732
 733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 734         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 735         { .dma_req = -1 }
 736 };
 737
 738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 739         .manager_count          = 3,
 740         .has_framedonetv_irq    = 1
 741 };
 742
 743 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 744         .name           = "dss_dispc",
 745         .class          = &omap44xx_dispc_hwmod_class,
 746         .clkdm_name     = "l3_dss_clkdm",
 747         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 748         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 749         .main_clk       = "dss_dss_clk",
 750         .prcm = {
 751                 .omap4 = {
 752                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 753                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 754                 },
 755         },
 756         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 757 };
 758
 759 /*
 760  * 'dsi' class
 761  * display serial interface controller
 762  */
 763
 764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 765         .rev_offs       = 0x0000,
 766         .sysc_offs      = 0x0010,
 767         .syss_offs      = 0x0014,
 768         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 769                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 770                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 772         .sysc_fields    = &omap_hwmod_sysc_type1,
 773 };
 774
 775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 776         .name   = "dsi",
 777         .sysc   = &omap44xx_dsi_sysc,
 778 };
 779
 780 /* dss_dsi1 */
 781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 782         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 783         { .irq = -1 }
 784 };
 785
 786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 787         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 788         { .dma_req = -1 }
 789 };
 790
 791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 792         { .role = "sys_clk", .clk = "dss_sys_clk" },
 793 };
 794
 795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 796         .name           = "dss_dsi1",
 797         .class          = &omap44xx_dsi_hwmod_class,
 798         .clkdm_name     = "l3_dss_clkdm",
 799         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 800         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 801         .main_clk       = "dss_dss_clk",
 802         .prcm = {
 803                 .omap4 = {
 804                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 805                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 806                 },
 807         },
 808         .opt_clks       = dss_dsi1_opt_clks,
 809         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 810 };
 811
 812 /* dss_dsi2 */
 813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 814         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 815         { .irq = -1 }
 816 };
 817
 818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 819         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 820         { .dma_req = -1 }
 821 };
 822
 823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 824         { .role = "sys_clk", .clk = "dss_sys_clk" },
 825 };
 826
 827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 828         .name           = "dss_dsi2",
 829         .class          = &omap44xx_dsi_hwmod_class,
 830         .clkdm_name     = "l3_dss_clkdm",
 831         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 832         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 833         .main_clk       = "dss_dss_clk",
 834         .prcm = {
 835                 .omap4 = {
 836                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 837                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 838                 },
 839         },
 840         .opt_clks       = dss_dsi2_opt_clks,
 841         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 842 };
 843
 844 /*
 845  * 'hdmi' class
 846  * hdmi controller
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x0010,
 852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 853                            SYSC_HAS_SOFTRESET),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 855                            SIDLE_SMART_WKUP),
 856         .sysc_fields    = &omap_hwmod_sysc_type2,
 857 };
 858
 859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 860         .name   = "hdmi",
 861         .sysc   = &omap44xx_hdmi_sysc,
 862 };
 863
 864 /* dss_hdmi */
 865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 866         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 867         { .irq = -1 }
 868 };
 869
 870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 871         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 872         { .dma_req = -1 }
 873 };
 874
 875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 876         { .role = "sys_clk", .clk = "dss_sys_clk" },
 877 };
 878
 879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 880         .name           = "dss_hdmi",
 881         .class          = &omap44xx_hdmi_hwmod_class,
 882         .clkdm_name     = "l3_dss_clkdm",
 883         /*
 884          * HDMI audio requires to use no-idle mode. Hence,
 885          * set idle mode by software.
 886          */
 887         .flags          = HWMOD_SWSUP_SIDLE,
 888         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 889         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 890         .main_clk       = "dss_48mhz_clk",
 891         .prcm = {
 892                 .omap4 = {
 893                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 894                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 895                 },
 896         },
 897         .opt_clks       = dss_hdmi_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 899 };
 900
 901 /*
 902  * 'rfbi' class
 903  * remote frame buffer interface
 904  */
 905
 906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 907         .rev_offs       = 0x0000,
 908         .sysc_offs      = 0x0010,
 909         .syss_offs      = 0x0014,
 910         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 911                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 912         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 913         .sysc_fields    = &omap_hwmod_sysc_type1,
 914 };
 915
 916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 917         .name   = "rfbi",
 918         .sysc   = &omap44xx_rfbi_sysc,
 919 };
 920
 921 /* dss_rfbi */
 922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 923         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 924         { .dma_req = -1 }
 925 };
 926
 927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 928         { .role = "ick", .clk = "dss_fck" },
 929 };
 930
 931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 932         .name           = "dss_rfbi",
 933         .class          = &omap44xx_rfbi_hwmod_class,
 934         .clkdm_name     = "l3_dss_clkdm",
 935         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 936         .main_clk       = "dss_dss_clk",
 937         .prcm = {
 938                 .omap4 = {
 939                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 940                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 941                 },
 942         },
 943         .opt_clks       = dss_rfbi_opt_clks,
 944         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 945 };
 946
 947 /*
 948  * 'venc' class
 949  * video encoder
 950  */
 951
 952 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 953         .name   = "venc",
 954 };
 955
 956 /* dss_venc */
 957 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 958         .name           = "dss_venc",
 959         .class          = &omap44xx_venc_hwmod_class,
 960         .clkdm_name     = "l3_dss_clkdm",
 961         .main_clk       = "dss_tv_clk",
 962         .prcm = {
 963                 .omap4 = {
 964                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 965                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 966                 },
 967         },
 968 };
 969
 970 /*
 971  * 'elm' class
 972  * bch error location module
 973  */
 974
 975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 976         .rev_offs       = 0x0000,
 977         .sysc_offs      = 0x0010,
 978         .syss_offs      = 0x0014,
 979         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 980                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 981                            SYSS_HAS_RESET_STATUS),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 987         .name   = "elm",
 988         .sysc   = &omap44xx_elm_sysc,
 989 };
 990
 991 /* elm */
 992 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 993         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 994         { .irq = -1 }
 995 };
 996
 997 static struct omap_hwmod omap44xx_elm_hwmod = {
 998         .name           = "elm",
 999         .class          = &omap44xx_elm_hwmod_class,
1000         .clkdm_name     = "l4_per_clkdm",
1001         .mpu_irqs       = omap44xx_elm_irqs,
1002         .prcm = {
1003                 .omap4 = {
1004                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1006                 },
1007         },
1008 };
1009
1010 /*
1011  * 'emif' class
1012  * external memory interface no1
1013  */
1014
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1016         .rev_offs       = 0x0000,
1017 };
1018
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1020         .name   = "emif",
1021         .sysc   = &omap44xx_emif_sysc,
1022 };
1023
1024 /* emif1 */
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1026         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1027         { .irq = -1 }
1028 };
1029
1030 static struct omap_hwmod omap44xx_emif1_hwmod = {
1031         .name           = "emif1",
1032         .class          = &omap44xx_emif_hwmod_class,
1033         .clkdm_name     = "l3_emif_clkdm",
1034         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1035         .mpu_irqs       = omap44xx_emif1_irqs,
1036         .main_clk       = "ddrphy_ck",
1037         .prcm = {
1038                 .omap4 = {
1039                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1040                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1041                         .modulemode   = MODULEMODE_HWCTRL,
1042                 },
1043         },
1044 };
1045
1046 /* emif2 */
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1048         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1049         { .irq = -1 }
1050 };
1051
1052 static struct omap_hwmod omap44xx_emif2_hwmod = {
1053         .name           = "emif2",
1054         .class          = &omap44xx_emif_hwmod_class,
1055         .clkdm_name     = "l3_emif_clkdm",
1056         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1057         .mpu_irqs       = omap44xx_emif2_irqs,
1058         .main_clk       = "ddrphy_ck",
1059         .prcm = {
1060                 .omap4 = {
1061                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1062                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1063                         .modulemode   = MODULEMODE_HWCTRL,
1064                 },
1065         },
1066 };
1067
1068 /*
1069  * 'fdif' class
1070  * face detection hw accelerator module
1071  */
1072
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1074         .rev_offs       = 0x0000,
1075         .sysc_offs      = 0x0010,
1076         /*
1077          * FDIF needs 100 OCP clk cycles delay after a softreset before
1078          * accessing sysconfig again.
1079          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1081          *
1082          * TODO: Indicate errata when available.
1083          */
1084         .srst_udelay    = 2,
1085         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1086                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089         .sysc_fields    = &omap_hwmod_sysc_type2,
1090 };
1091
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1093         .name   = "fdif",
1094         .sysc   = &omap44xx_fdif_sysc,
1095 };
1096
1097 /* fdif */
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1099         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1100         { .irq = -1 }
1101 };
1102
1103 static struct omap_hwmod omap44xx_fdif_hwmod = {
1104         .name           = "fdif",
1105         .class          = &omap44xx_fdif_hwmod_class,
1106         .clkdm_name     = "iss_clkdm",
1107         .mpu_irqs       = omap44xx_fdif_irqs,
1108         .main_clk       = "fdif_fck",
1109         .prcm = {
1110                 .omap4 = {
1111                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1112                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1113                         .modulemode   = MODULEMODE_SWCTRL,
1114                 },
1115         },
1116 };
1117
1118 /*
1119  * 'gpio' class
1120  * general purpose io module
1121  */
1122
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1124         .rev_offs       = 0x0000,
1125         .sysc_offs      = 0x0010,
1126         .syss_offs      = 0x0114,
1127         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1129                            SYSS_HAS_RESET_STATUS),
1130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1131                            SIDLE_SMART_WKUP),
1132         .sysc_fields    = &omap_hwmod_sysc_type1,
1133 };
1134
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1136         .name   = "gpio",
1137         .sysc   = &omap44xx_gpio_sysc,
1138         .rev    = 2,
1139 };
1140
1141 /* gpio dev_attr */
1142 static struct omap_gpio_dev_attr gpio_dev_attr = {
1143         .bank_width     = 32,
1144         .dbck_flag      = true,
1145 };
1146
1147 /* gpio1 */
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1149         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1150         { .irq = -1 }
1151 };
1152
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1154         { .role = "dbclk", .clk = "gpio1_dbclk" },
1155 };
1156
1157 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1158         .name           = "gpio1",
1159         .class          = &omap44xx_gpio_hwmod_class,
1160         .clkdm_name     = "l4_wkup_clkdm",
1161         .mpu_irqs       = omap44xx_gpio1_irqs,
1162         .main_clk       = "gpio1_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .opt_clks       = gpio1_opt_clks,
1171         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1172         .dev_attr       = &gpio_dev_attr,
1173 };
1174
1175 /* gpio2 */
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1177         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1178         { .irq = -1 }
1179 };
1180
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1182         { .role = "dbclk", .clk = "gpio2_dbclk" },
1183 };
1184
1185 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1186         .name           = "gpio2",
1187         .class          = &omap44xx_gpio_hwmod_class,
1188         .clkdm_name     = "l4_per_clkdm",
1189         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190         .mpu_irqs       = omap44xx_gpio2_irqs,
1191         .main_clk       = "gpio2_ick",
1192         .prcm = {
1193                 .omap4 = {
1194                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1195                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1196                         .modulemode   = MODULEMODE_HWCTRL,
1197                 },
1198         },
1199         .opt_clks       = gpio2_opt_clks,
1200         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1201         .dev_attr       = &gpio_dev_attr,
1202 };
1203
1204 /* gpio3 */
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1206         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1207         { .irq = -1 }
1208 };
1209
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1211         { .role = "dbclk", .clk = "gpio3_dbclk" },
1212 };
1213
1214 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1215         .name           = "gpio3",
1216         .class          = &omap44xx_gpio_hwmod_class,
1217         .clkdm_name     = "l4_per_clkdm",
1218         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219         .mpu_irqs       = omap44xx_gpio3_irqs,
1220         .main_clk       = "gpio3_ick",
1221         .prcm = {
1222                 .omap4 = {
1223                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1224                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1225                         .modulemode   = MODULEMODE_HWCTRL,
1226                 },
1227         },
1228         .opt_clks       = gpio3_opt_clks,
1229         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1230         .dev_attr       = &gpio_dev_attr,
1231 };
1232
1233 /* gpio4 */
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1235         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1236         { .irq = -1 }
1237 };
1238
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1240         { .role = "dbclk", .clk = "gpio4_dbclk" },
1241 };
1242
1243 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1244         .name           = "gpio4",
1245         .class          = &omap44xx_gpio_hwmod_class,
1246         .clkdm_name     = "l4_per_clkdm",
1247         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248         .mpu_irqs       = omap44xx_gpio4_irqs,
1249         .main_clk       = "gpio4_ick",
1250         .prcm = {
1251                 .omap4 = {
1252                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1253                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1254                         .modulemode   = MODULEMODE_HWCTRL,
1255                 },
1256         },
1257         .opt_clks       = gpio4_opt_clks,
1258         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1259         .dev_attr       = &gpio_dev_attr,
1260 };
1261
1262 /* gpio5 */
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1264         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1265         { .irq = -1 }
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1269         { .role = "dbclk", .clk = "gpio5_dbclk" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1273         .name           = "gpio5",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .clkdm_name     = "l4_per_clkdm",
1276         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277         .mpu_irqs       = omap44xx_gpio5_irqs,
1278         .main_clk       = "gpio5_ick",
1279         .prcm = {
1280                 .omap4 = {
1281                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1282                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1283                         .modulemode   = MODULEMODE_HWCTRL,
1284                 },
1285         },
1286         .opt_clks       = gpio5_opt_clks,
1287         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1288         .dev_attr       = &gpio_dev_attr,
1289 };
1290
1291 /* gpio6 */
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1293         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1294         { .irq = -1 }
1295 };
1296
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1298         { .role = "dbclk", .clk = "gpio6_dbclk" },
1299 };
1300
1301 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1302         .name           = "gpio6",
1303         .class          = &omap44xx_gpio_hwmod_class,
1304         .clkdm_name     = "l4_per_clkdm",
1305         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1306         .mpu_irqs       = omap44xx_gpio6_irqs,
1307         .main_clk       = "gpio6_ick",
1308         .prcm = {
1309                 .omap4 = {
1310                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1311                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1312                         .modulemode   = MODULEMODE_HWCTRL,
1313                 },
1314         },
1315         .opt_clks       = gpio6_opt_clks,
1316         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1317         .dev_attr       = &gpio_dev_attr,
1318 };
1319
1320 /*
1321  * 'gpmc' class
1322  * general purpose memory controller
1323  */
1324
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1326         .rev_offs       = 0x0000,
1327         .sysc_offs      = 0x0010,
1328         .syss_offs      = 0x0014,
1329         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1330                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332         .sysc_fields    = &omap_hwmod_sysc_type1,
1333 };
1334
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1336         .name   = "gpmc",
1337         .sysc   = &omap44xx_gpmc_sysc,
1338 };
1339
1340 /* gpmc */
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1342         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1343         { .irq = -1 }
1344 };
1345
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1347         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1348         { .dma_req = -1 }
1349 };
1350
1351 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1352         .name           = "gpmc",
1353         .class          = &omap44xx_gpmc_hwmod_class,
1354         .clkdm_name     = "l3_2_clkdm",
1355         /*
1356          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1357          * block.  It is not being added due to any known bugs with
1358          * resetting the GPMC IP block, but rather because any timings
1359          * set by the bootloader are not being correctly programmed by
1360          * the kernel from the board file or DT data.
1361          * HWMOD_INIT_NO_RESET should be removed ASAP.
1362          */
1363         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1364         .mpu_irqs       = omap44xx_gpmc_irqs,
1365         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1366         .prcm = {
1367                 .omap4 = {
1368                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1369                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1370                         .modulemode   = MODULEMODE_HWCTRL,
1371                 },
1372         },
1373 };
1374
1375 /*
1376  * 'gpu' class
1377  * 2d/3d graphics accelerator
1378  */
1379
1380 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1381         .rev_offs       = 0x1fc00,
1382         .sysc_offs      = 0x1fc10,
1383         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1385                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1386                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1387         .sysc_fields    = &omap_hwmod_sysc_type2,
1388 };
1389
1390 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1391         .name   = "gpu",
1392         .sysc   = &omap44xx_gpu_sysc,
1393 };
1394
1395 /* gpu */
1396 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1397         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1398         { .irq = -1 }
1399 };
1400
1401 static struct omap_hwmod omap44xx_gpu_hwmod = {
1402         .name           = "gpu",
1403         .class          = &omap44xx_gpu_hwmod_class,
1404         .clkdm_name     = "l3_gfx_clkdm",
1405         .mpu_irqs       = omap44xx_gpu_irqs,
1406         .main_clk       = "gpu_fck",
1407         .prcm = {
1408                 .omap4 = {
1409                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1410                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1411                         .modulemode   = MODULEMODE_SWCTRL,
1412                 },
1413         },
1414 };
1415
1416 /*
1417  * 'hdq1w' class
1418  * hdq / 1-wire serial interface controller
1419  */
1420
1421 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1422         .rev_offs       = 0x0000,
1423         .sysc_offs      = 0x0014,
1424         .syss_offs      = 0x0018,
1425         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1426                            SYSS_HAS_RESET_STATUS),
1427         .sysc_fields    = &omap_hwmod_sysc_type1,
1428 };
1429
1430 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1431         .name   = "hdq1w",
1432         .sysc   = &omap44xx_hdq1w_sysc,
1433 };
1434
1435 /* hdq1w */
1436 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1437         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1438         { .irq = -1 }
1439 };
1440
1441 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1442         .name           = "hdq1w",
1443         .class          = &omap44xx_hdq1w_hwmod_class,
1444         .clkdm_name     = "l4_per_clkdm",
1445         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1446         .mpu_irqs       = omap44xx_hdq1w_irqs,
1447         .main_clk       = "hdq1w_fck",
1448         .prcm = {
1449                 .omap4 = {
1450                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1451                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1452                         .modulemode   = MODULEMODE_SWCTRL,
1453                 },
1454         },
1455 };
1456
1457 /*
1458  * 'hsi' class
1459  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1460  * serial if)
1461  */
1462
1463 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1464         .rev_offs       = 0x0000,
1465         .sysc_offs      = 0x0010,
1466         .syss_offs      = 0x0014,
1467         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1468                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1469                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1470         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1471                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1472                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1473         .sysc_fields    = &omap_hwmod_sysc_type1,
1474 };
1475
1476 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1477         .name   = "hsi",
1478         .sysc   = &omap44xx_hsi_sysc,
1479 };
1480
1481 /* hsi */
1482 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1483         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1484         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1485         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1486         { .irq = -1 }
1487 };
1488
1489 static struct omap_hwmod omap44xx_hsi_hwmod = {
1490         .name           = "hsi",
1491         .class          = &omap44xx_hsi_hwmod_class,
1492         .clkdm_name     = "l3_init_clkdm",
1493         .mpu_irqs       = omap44xx_hsi_irqs,
1494         .main_clk       = "hsi_fck",
1495         .prcm = {
1496                 .omap4 = {
1497                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1498                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1499                         .modulemode   = MODULEMODE_HWCTRL,
1500                 },
1501         },
1502 };
1503
1504 /*
1505  * 'i2c' class
1506  * multimaster high-speed i2c controller
1507  */
1508
1509 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1510         .sysc_offs      = 0x0010,
1511         .syss_offs      = 0x0090,
1512         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1513                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1514                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1515         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1516                            SIDLE_SMART_WKUP),
1517         .clockact       = CLOCKACT_TEST_ICLK,
1518         .sysc_fields    = &omap_hwmod_sysc_type1,
1519 };
1520
1521 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1522         .name   = "i2c",
1523         .sysc   = &omap44xx_i2c_sysc,
1524         .rev    = OMAP_I2C_IP_VERSION_2,
1525         .reset  = &omap_i2c_reset,
1526 };
1527
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1530                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1531 };
1532
1533 /* i2c1 */
1534 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1535         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1536         { .irq = -1 }
1537 };
1538
1539 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1540         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1541         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1542         { .dma_req = -1 }
1543 };
1544
1545 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1546         .name           = "i2c1",
1547         .class          = &omap44xx_i2c_hwmod_class,
1548         .clkdm_name     = "l4_per_clkdm",
1549         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1550         .mpu_irqs       = omap44xx_i2c1_irqs,
1551         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1552         .main_clk       = "i2c1_fck",
1553         .prcm = {
1554                 .omap4 = {
1555                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1556                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1557                         .modulemode   = MODULEMODE_SWCTRL,
1558                 },
1559         },
1560         .dev_attr       = &i2c_dev_attr,
1561 };
1562
1563 /* i2c2 */
1564 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1565         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1566         { .irq = -1 }
1567 };
1568
1569 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1570         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1571         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1572         { .dma_req = -1 }
1573 };
1574
1575 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1576         .name           = "i2c2",
1577         .class          = &omap44xx_i2c_hwmod_class,
1578         .clkdm_name     = "l4_per_clkdm",
1579         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1580         .mpu_irqs       = omap44xx_i2c2_irqs,
1581         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1582         .main_clk       = "i2c2_fck",
1583         .prcm = {
1584                 .omap4 = {
1585                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1586                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1587                         .modulemode   = MODULEMODE_SWCTRL,
1588                 },
1589         },
1590         .dev_attr       = &i2c_dev_attr,
1591 };
1592
1593 /* i2c3 */
1594 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1595         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1596         { .irq = -1 }
1597 };
1598
1599 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1600         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1601         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1602         { .dma_req = -1 }
1603 };
1604
1605 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1606         .name           = "i2c3",
1607         .class          = &omap44xx_i2c_hwmod_class,
1608         .clkdm_name     = "l4_per_clkdm",
1609         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1610         .mpu_irqs       = omap44xx_i2c3_irqs,
1611         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1612         .main_clk       = "i2c3_fck",
1613         .prcm = {
1614                 .omap4 = {
1615                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1616                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1617                         .modulemode   = MODULEMODE_SWCTRL,
1618                 },
1619         },
1620         .dev_attr       = &i2c_dev_attr,
1621 };
1622
1623 /* i2c4 */
1624 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1625         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1626         { .irq = -1 }
1627 };
1628
1629 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1630         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1631         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1632         { .dma_req = -1 }
1633 };
1634
1635 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1636         .name           = "i2c4",
1637         .class          = &omap44xx_i2c_hwmod_class,
1638         .clkdm_name     = "l4_per_clkdm",
1639         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1640         .mpu_irqs       = omap44xx_i2c4_irqs,
1641         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1642         .main_clk       = "i2c4_fck",
1643         .prcm = {
1644                 .omap4 = {
1645                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1646                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1647                         .modulemode   = MODULEMODE_SWCTRL,
1648                 },
1649         },
1650         .dev_attr       = &i2c_dev_attr,
1651 };
1652
1653 /*
1654  * 'ipu' class
1655  * imaging processor unit
1656  */
1657
1658 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1659         .name   = "ipu",
1660 };
1661
1662 /* ipu */
1663 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1664         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1665         { .irq = -1 }
1666 };
1667
1668 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1669         { .name = "cpu0", .rst_shift = 0 },
1670         { .name = "cpu1", .rst_shift = 1 },
1671 };
1672
1673 static struct omap_hwmod omap44xx_ipu_hwmod = {
1674         .name           = "ipu",
1675         .class          = &omap44xx_ipu_hwmod_class,
1676         .clkdm_name     = "ducati_clkdm",
1677         .mpu_irqs       = omap44xx_ipu_irqs,
1678         .rst_lines      = omap44xx_ipu_resets,
1679         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1680         .main_clk       = "ipu_fck",
1681         .prcm = {
1682                 .omap4 = {
1683                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1684                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1685                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1686                         .modulemode   = MODULEMODE_HWCTRL,
1687                 },
1688         },
1689 };
1690
1691 /*
1692  * 'iss' class
1693  * external images sensor pixel data processor
1694  */
1695
1696 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1697         .rev_offs       = 0x0000,
1698         .sysc_offs      = 0x0010,
1699         /*
1700          * ISS needs 100 OCP clk cycles delay after a softreset before
1701          * accessing sysconfig again.
1702          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1703          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1704          *
1705          * TODO: Indicate errata when available.
1706          */
1707         .srst_udelay    = 2,
1708         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1709                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1710         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1711                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1712                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1713         .sysc_fields    = &omap_hwmod_sysc_type2,
1714 };
1715
1716 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1717         .name   = "iss",
1718         .sysc   = &omap44xx_iss_sysc,
1719 };
1720
1721 /* iss */
1722 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1723         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1724         { .irq = -1 }
1725 };
1726
1727 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1728         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1729         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1730         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1731         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1732         { .dma_req = -1 }
1733 };
1734
1735 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1736         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1737 };
1738
1739 static struct omap_hwmod omap44xx_iss_hwmod = {
1740         .name           = "iss",
1741         .class          = &omap44xx_iss_hwmod_class,
1742         .clkdm_name     = "iss_clkdm",
1743         .mpu_irqs       = omap44xx_iss_irqs,
1744         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1745         .main_clk       = "iss_fck",
1746         .prcm = {
1747                 .omap4 = {
1748                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1749                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1750                         .modulemode   = MODULEMODE_SWCTRL,
1751                 },
1752         },
1753         .opt_clks       = iss_opt_clks,
1754         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1755 };
1756
1757 /*
1758  * 'iva' class
1759  * multi-standard video encoder/decoder hardware accelerator
1760  */
1761
1762 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1763         .name   = "iva",
1764 };
1765
1766 /* iva */
1767 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1768         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1769         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1771         { .irq = -1 }
1772 };
1773
1774 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1775         { .name = "seq0", .rst_shift = 0 },
1776         { .name = "seq1", .rst_shift = 1 },
1777         { .name = "logic", .rst_shift = 2 },
1778 };
1779
1780 static struct omap_hwmod omap44xx_iva_hwmod = {
1781         .name           = "iva",
1782         .class          = &omap44xx_iva_hwmod_class,
1783         .clkdm_name     = "ivahd_clkdm",
1784         .mpu_irqs       = omap44xx_iva_irqs,
1785         .rst_lines      = omap44xx_iva_resets,
1786         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1787         .main_clk       = "iva_fck",
1788         .prcm = {
1789                 .omap4 = {
1790                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1791                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1792                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1793                         .modulemode   = MODULEMODE_HWCTRL,
1794                 },
1795         },
1796 };
1797
1798 /*
1799  * 'kbd' class
1800  * keyboard controller
1801  */
1802
1803 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1804         .rev_offs       = 0x0000,
1805         .sysc_offs      = 0x0010,
1806         .syss_offs      = 0x0014,
1807         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1808                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1809                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1810                            SYSS_HAS_RESET_STATUS),
1811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1812         .sysc_fields    = &omap_hwmod_sysc_type1,
1813 };
1814
1815 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1816         .name   = "kbd",
1817         .sysc   = &omap44xx_kbd_sysc,
1818 };
1819
1820 /* kbd */
1821 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1822         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1823         { .irq = -1 }
1824 };
1825
1826 static struct omap_hwmod omap44xx_kbd_hwmod = {
1827         .name           = "kbd",
1828         .class          = &omap44xx_kbd_hwmod_class,
1829         .clkdm_name     = "l4_wkup_clkdm",
1830         .mpu_irqs       = omap44xx_kbd_irqs,
1831         .main_clk       = "kbd_fck",
1832         .prcm = {
1833                 .omap4 = {
1834                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1835                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1836                         .modulemode   = MODULEMODE_SWCTRL,
1837                 },
1838         },
1839 };
1840
1841 /*
1842  * 'mailbox' class
1843  * mailbox module allowing communication between the on-chip processors using a
1844  * queued mailbox-interrupt mechanism.
1845  */
1846
1847 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1848         .rev_offs       = 0x0000,
1849         .sysc_offs      = 0x0010,
1850         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1851                            SYSC_HAS_SOFTRESET),
1852         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1853         .sysc_fields    = &omap_hwmod_sysc_type2,
1854 };
1855
1856 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1857         .name   = "mailbox",
1858         .sysc   = &omap44xx_mailbox_sysc,
1859 };
1860
1861 /* mailbox */
1862 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1863         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1864         { .irq = -1 }
1865 };
1866
1867 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1868         .name           = "mailbox",
1869         .class          = &omap44xx_mailbox_hwmod_class,
1870         .clkdm_name     = "l4_cfg_clkdm",
1871         .mpu_irqs       = omap44xx_mailbox_irqs,
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1875                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1876                 },
1877         },
1878 };
1879
1880 /*
1881  * 'mcasp' class
1882  * multi-channel audio serial port controller
1883  */
1884
1885 /* The IP is not compliant to type1 / type2 scheme */
1886 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1887         .sidle_shift    = 0,
1888 };
1889
1890 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1891         .sysc_offs      = 0x0004,
1892         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1893         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1894                            SIDLE_SMART_WKUP),
1895         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1896 };
1897
1898 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1899         .name   = "mcasp",
1900         .sysc   = &omap44xx_mcasp_sysc,
1901 };
1902
1903 /* mcasp */
1904 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1905         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1906         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1907         { .irq = -1 }
1908 };
1909
1910 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1911         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1912         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1913         { .dma_req = -1 }
1914 };
1915
1916 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1917         .name           = "mcasp",
1918         .class          = &omap44xx_mcasp_hwmod_class,
1919         .clkdm_name     = "abe_clkdm",
1920         .mpu_irqs       = omap44xx_mcasp_irqs,
1921         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1922         .main_clk       = "mcasp_fck",
1923         .prcm = {
1924                 .omap4 = {
1925                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1926                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1927                         .modulemode   = MODULEMODE_SWCTRL,
1928                 },
1929         },
1930 };
1931
1932 /*
1933  * 'mcbsp' class
1934  * multi channel buffered serial port controller
1935  */
1936
1937 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1938         .sysc_offs      = 0x008c,
1939         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1940                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1942         .sysc_fields    = &omap_hwmod_sysc_type1,
1943 };
1944
1945 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1946         .name   = "mcbsp",
1947         .sysc   = &omap44xx_mcbsp_sysc,
1948         .rev    = MCBSP_CONFIG_TYPE4,
1949 };
1950
1951 /* mcbsp1 */
1952 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1953         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1954         { .irq = -1 }
1955 };
1956
1957 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1958         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1959         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1960         { .dma_req = -1 }
1961 };
1962
1963 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1964         { .role = "pad_fck", .clk = "pad_clks_ck" },
1965         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1966 };
1967
1968 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1969         .name           = "mcbsp1",
1970         .class          = &omap44xx_mcbsp_hwmod_class,
1971         .clkdm_name     = "abe_clkdm",
1972         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1973         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1974         .main_clk       = "mcbsp1_fck",
1975         .prcm = {
1976                 .omap4 = {
1977                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1978                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1979                         .modulemode   = MODULEMODE_SWCTRL,
1980                 },
1981         },
1982         .opt_clks       = mcbsp1_opt_clks,
1983         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1984 };
1985
1986 /* mcbsp2 */
1987 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1988         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1989         { .irq = -1 }
1990 };
1991
1992 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1993         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1994         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1995         { .dma_req = -1 }
1996 };
1997
1998 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1999         { .role = "pad_fck", .clk = "pad_clks_ck" },
2000         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2001 };
2002
2003 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2004         .name           = "mcbsp2",
2005         .class          = &omap44xx_mcbsp_hwmod_class,
2006         .clkdm_name     = "abe_clkdm",
2007         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2008         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2009         .main_clk       = "mcbsp2_fck",
2010         .prcm = {
2011                 .omap4 = {
2012                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2013                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2014                         .modulemode   = MODULEMODE_SWCTRL,
2015                 },
2016         },
2017         .opt_clks       = mcbsp2_opt_clks,
2018         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2019 };
2020
2021 /* mcbsp3 */
2022 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2023         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2024         { .irq = -1 }
2025 };
2026
2027 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2028         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2029         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2030         { .dma_req = -1 }
2031 };
2032
2033 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2034         { .role = "pad_fck", .clk = "pad_clks_ck" },
2035         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2036 };
2037
2038 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2039         .name           = "mcbsp3",
2040         .class          = &omap44xx_mcbsp_hwmod_class,
2041         .clkdm_name     = "abe_clkdm",
2042         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2043         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2044         .main_clk       = "mcbsp3_fck",
2045         .prcm = {
2046                 .omap4 = {
2047                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2048                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2049                         .modulemode   = MODULEMODE_SWCTRL,
2050                 },
2051         },
2052         .opt_clks       = mcbsp3_opt_clks,
2053         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2054 };
2055
2056 /* mcbsp4 */
2057 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2058         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2059         { .irq = -1 }
2060 };
2061
2062 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2063         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2064         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2065         { .dma_req = -1 }
2066 };
2067
2068 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2069         { .role = "pad_fck", .clk = "pad_clks_ck" },
2070         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2071 };
2072
2073 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2074         .name           = "mcbsp4",
2075         .class          = &omap44xx_mcbsp_hwmod_class,
2076         .clkdm_name     = "l4_per_clkdm",
2077         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2078         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2079         .main_clk       = "mcbsp4_fck",
2080         .prcm = {
2081                 .omap4 = {
2082                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2083                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2084                         .modulemode   = MODULEMODE_SWCTRL,
2085                 },
2086         },
2087         .opt_clks       = mcbsp4_opt_clks,
2088         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2089 };
2090
2091 /*
2092  * 'mcpdm' class
2093  * multi channel pdm controller (proprietary interface with phoenix power
2094  * ic)
2095  */
2096
2097 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2098         .rev_offs       = 0x0000,
2099         .sysc_offs      = 0x0010,
2100         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2101                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2102         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2103                            SIDLE_SMART_WKUP),
2104         .sysc_fields    = &omap_hwmod_sysc_type2,
2105 };
2106
2107 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2108         .name   = "mcpdm",
2109         .sysc   = &omap44xx_mcpdm_sysc,
2110 };
2111
2112 /* mcpdm */
2113 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2114         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2115         { .irq = -1 }
2116 };
2117
2118 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2119         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2120         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2121         { .dma_req = -1 }
2122 };
2123
2124 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2125         .name           = "mcpdm",
2126         .class          = &omap44xx_mcpdm_hwmod_class,
2127         .clkdm_name     = "abe_clkdm",
2128         .mpu_irqs       = omap44xx_mcpdm_irqs,
2129         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2130         .main_clk       = "mcpdm_fck",
2131         .prcm = {
2132                 .omap4 = {
2133                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2134                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2135                         .modulemode   = MODULEMODE_SWCTRL,
2136                 },
2137         },
2138 };
2139
2140 /*
2141  * 'mcspi' class
2142  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2143  * bus
2144  */
2145
2146 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2147         .rev_offs       = 0x0000,
2148         .sysc_offs      = 0x0010,
2149         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2150                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2152                            SIDLE_SMART_WKUP),
2153         .sysc_fields    = &omap_hwmod_sysc_type2,
2154 };
2155
2156 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2157         .name   = "mcspi",
2158         .sysc   = &omap44xx_mcspi_sysc,
2159         .rev    = OMAP4_MCSPI_REV,
2160 };
2161
2162 /* mcspi1 */
2163 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2164         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2165         { .irq = -1 }
2166 };
2167
2168 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2169         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2170         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2171         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2172         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2173         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2174         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2175         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2176         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2177         { .dma_req = -1 }
2178 };
2179
2180 /* mcspi1 dev_attr */
2181 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2182         .num_chipselect = 4,
2183 };
2184
2185 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2186         .name           = "mcspi1",
2187         .class          = &omap44xx_mcspi_hwmod_class,
2188         .clkdm_name     = "l4_per_clkdm",
2189         .mpu_irqs       = omap44xx_mcspi1_irqs,
2190         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2191         .main_clk       = "mcspi1_fck",
2192         .prcm = {
2193                 .omap4 = {
2194                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2195                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2196                         .modulemode   = MODULEMODE_SWCTRL,
2197                 },
2198         },
2199         .dev_attr       = &mcspi1_dev_attr,
2200 };
2201
2202 /* mcspi2 */
2203 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2204         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2205         { .irq = -1 }
2206 };
2207
2208 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2209         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2210         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2211         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2212         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2213         { .dma_req = -1 }
2214 };
2215
2216 /* mcspi2 dev_attr */
2217 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2218         .num_chipselect = 2,
2219 };
2220
2221 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2222         .name           = "mcspi2",
2223         .class          = &omap44xx_mcspi_hwmod_class,
2224         .clkdm_name     = "l4_per_clkdm",
2225         .mpu_irqs       = omap44xx_mcspi2_irqs,
2226         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2227         .main_clk       = "mcspi2_fck",
2228         .prcm = {
2229                 .omap4 = {
2230                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2231                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2232                         .modulemode   = MODULEMODE_SWCTRL,
2233                 },
2234         },
2235         .dev_attr       = &mcspi2_dev_attr,
2236 };
2237
2238 /* mcspi3 */
2239 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2240         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2241         { .irq = -1 }
2242 };
2243
2244 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2245         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2246         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2247         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2248         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2249         { .dma_req = -1 }
2250 };
2251
2252 /* mcspi3 dev_attr */
2253 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2254         .num_chipselect = 2,
2255 };
2256
2257 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2258         .name           = "mcspi3",
2259         .class          = &omap44xx_mcspi_hwmod_class,
2260         .clkdm_name     = "l4_per_clkdm",
2261         .mpu_irqs       = omap44xx_mcspi3_irqs,
2262         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2263         .main_clk       = "mcspi3_fck",
2264         .prcm = {
2265                 .omap4 = {
2266                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2267                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2268                         .modulemode   = MODULEMODE_SWCTRL,
2269                 },
2270         },
2271         .dev_attr       = &mcspi3_dev_attr,
2272 };
2273
2274 /* mcspi4 */
2275 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2276         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2277         { .irq = -1 }
2278 };
2279
2280 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2281         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2282         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2283         { .dma_req = -1 }
2284 };
2285
2286 /* mcspi4 dev_attr */
2287 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2288         .num_chipselect = 1,
2289 };
2290
2291 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2292         .name           = "mcspi4",
2293         .class          = &omap44xx_mcspi_hwmod_class,
2294         .clkdm_name     = "l4_per_clkdm",
2295         .mpu_irqs       = omap44xx_mcspi4_irqs,
2296         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2297         .main_clk       = "mcspi4_fck",
2298         .prcm = {
2299                 .omap4 = {
2300                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2301                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2302                         .modulemode   = MODULEMODE_SWCTRL,
2303                 },
2304         },
2305         .dev_attr       = &mcspi4_dev_attr,
2306 };
2307
2308 /*
2309  * 'mmc' class
2310  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2311  */
2312
2313 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2314         .rev_offs       = 0x0000,
2315         .sysc_offs      = 0x0010,
2316         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2317                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2318                            SYSC_HAS_SOFTRESET),
2319         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2320                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2321                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2322         .sysc_fields    = &omap_hwmod_sysc_type2,
2323 };
2324
2325 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2326         .name   = "mmc",
2327         .sysc   = &omap44xx_mmc_sysc,
2328 };
2329
2330 /* mmc1 */
2331 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2332         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2333         { .irq = -1 }
2334 };
2335
2336 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2337         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2338         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2339         { .dma_req = -1 }
2340 };
2341
2342 /* mmc1 dev_attr */
2343 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2344         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2345 };
2346
2347 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2348         .name           = "mmc1",
2349         .class          = &omap44xx_mmc_hwmod_class,
2350         .clkdm_name     = "l3_init_clkdm",
2351         .mpu_irqs       = omap44xx_mmc1_irqs,
2352         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2353         .main_clk       = "mmc1_fck",
2354         .prcm = {
2355                 .omap4 = {
2356                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2357                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2358                         .modulemode   = MODULEMODE_SWCTRL,
2359                 },
2360         },
2361         .dev_attr       = &mmc1_dev_attr,
2362 };
2363
2364 /* mmc2 */
2365 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2366         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2367         { .irq = -1 }
2368 };
2369
2370 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2371         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2372         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2373         { .dma_req = -1 }
2374 };
2375
2376 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2377         .name           = "mmc2",
2378         .class          = &omap44xx_mmc_hwmod_class,
2379         .clkdm_name     = "l3_init_clkdm",
2380         .mpu_irqs       = omap44xx_mmc2_irqs,
2381         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2382         .main_clk       = "mmc2_fck",
2383         .prcm = {
2384                 .omap4 = {
2385                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2386                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2387                         .modulemode   = MODULEMODE_SWCTRL,
2388                 },
2389         },
2390 };
2391
2392 /* mmc3 */
2393 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2394         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2395         { .irq = -1 }
2396 };
2397
2398 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2399         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2400         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2401         { .dma_req = -1 }
2402 };
2403
2404 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2405         .name           = "mmc3",
2406         .class          = &omap44xx_mmc_hwmod_class,
2407         .clkdm_name     = "l4_per_clkdm",
2408         .mpu_irqs       = omap44xx_mmc3_irqs,
2409         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2410         .main_clk       = "mmc3_fck",
2411         .prcm = {
2412                 .omap4 = {
2413                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2414                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2415                         .modulemode   = MODULEMODE_SWCTRL,
2416                 },
2417         },
2418 };
2419
2420 /* mmc4 */
2421 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2422         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2423         { .irq = -1 }
2424 };
2425
2426 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2427         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2428         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2429         { .dma_req = -1 }
2430 };
2431
2432 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2433         .name           = "mmc4",
2434         .class          = &omap44xx_mmc_hwmod_class,
2435         .clkdm_name     = "l4_per_clkdm",
2436         .mpu_irqs       = omap44xx_mmc4_irqs,
2437         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2438         .main_clk       = "mmc4_fck",
2439         .prcm = {
2440                 .omap4 = {
2441                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2442                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2443                         .modulemode   = MODULEMODE_SWCTRL,
2444                 },
2445         },
2446 };
2447
2448 /* mmc5 */
2449 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2450         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2451         { .irq = -1 }
2452 };
2453
2454 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2455         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2456         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2457         { .dma_req = -1 }
2458 };
2459
2460 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2461         .name           = "mmc5",
2462         .class          = &omap44xx_mmc_hwmod_class,
2463         .clkdm_name     = "l4_per_clkdm",
2464         .mpu_irqs       = omap44xx_mmc5_irqs,
2465         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2466         .main_clk       = "mmc5_fck",
2467         .prcm = {
2468                 .omap4 = {
2469                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2470                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2471                         .modulemode   = MODULEMODE_SWCTRL,
2472                 },
2473         },
2474 };
2475
2476 /*
2477  * 'mmu' class
2478  * The memory management unit performs virtual to physical address translation
2479  * for its requestors.
2480  */
2481
2482 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2483         .rev_offs       = 0x000,
2484         .sysc_offs      = 0x010,
2485         .syss_offs      = 0x014,
2486         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2487                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2488         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2489         .sysc_fields    = &omap_hwmod_sysc_type1,
2490 };
2491
2492 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2493         .name = "mmu",
2494         .sysc = &mmu_sysc,
2495 };
2496
2497 /* mmu ipu */
2498
2499 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2500         .da_start       = 0x0,
2501         .da_end         = 0xfffff000,
2502         .nr_tlb_entries = 32,
2503 };
2504
2505 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2506 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2507         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2508         { .irq = -1 }
2509 };
2510
2511 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2512         { .name = "mmu_cache", .rst_shift = 2 },
2513 };
2514
2515 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2516         {
2517                 .pa_start       = 0x55082000,
2518                 .pa_end         = 0x550820ff,
2519                 .flags          = ADDR_TYPE_RT,
2520         },
2521         { }
2522 };
2523
2524 /* l3_main_2 -> mmu_ipu */
2525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2526         .master         = &omap44xx_l3_main_2_hwmod,
2527         .slave          = &omap44xx_mmu_ipu_hwmod,
2528         .clk            = "l3_div_ck",
2529         .addr           = omap44xx_mmu_ipu_addrs,
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2534         .name           = "mmu_ipu",
2535         .class          = &omap44xx_mmu_hwmod_class,
2536         .clkdm_name     = "ducati_clkdm",
2537         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2538         .rst_lines      = omap44xx_mmu_ipu_resets,
2539         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2540         .main_clk       = "ducati_clk_mux_ck",
2541         .prcm = {
2542                 .omap4 = {
2543                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2544                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2545                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2546                         .modulemode   = MODULEMODE_HWCTRL,
2547                 },
2548         },
2549         .dev_attr       = &mmu_ipu_dev_attr,
2550 };
2551
2552 /* mmu dsp */
2553
2554 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2555         .da_start       = 0x0,
2556         .da_end         = 0xfffff000,
2557         .nr_tlb_entries = 32,
2558 };
2559
2560 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2561 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2562         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2563         { .irq = -1 }
2564 };
2565
2566 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2567         { .name = "mmu_cache", .rst_shift = 1 },
2568 };
2569
2570 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2571         {
2572                 .pa_start       = 0x4a066000,
2573                 .pa_end         = 0x4a0660ff,
2574                 .flags          = ADDR_TYPE_RT,
2575         },
2576         { }
2577 };
2578
2579 /* l4_cfg -> dsp */
2580 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2581         .master         = &omap44xx_l4_cfg_hwmod,
2582         .slave          = &omap44xx_mmu_dsp_hwmod,
2583         .clk            = "l4_div_ck",
2584         .addr           = omap44xx_mmu_dsp_addrs,
2585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2589         .name           = "mmu_dsp",
2590         .class          = &omap44xx_mmu_hwmod_class,
2591         .clkdm_name     = "tesla_clkdm",
2592         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2593         .rst_lines      = omap44xx_mmu_dsp_resets,
2594         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2595         .main_clk       = "dpll_iva_m4x2_ck",
2596         .prcm = {
2597                 .omap4 = {
2598                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2599                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2600                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2601                         .modulemode   = MODULEMODE_HWCTRL,
2602                 },
2603         },
2604         .dev_attr       = &mmu_dsp_dev_attr,
2605 };
2606
2607 /*
2608  * 'mpu' class
2609  * mpu sub-system
2610  */
2611
2612 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2613         .name   = "mpu",
2614 };
2615
2616 /* mpu */
2617 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2618         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2619         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2620         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2621         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2623         { .irq = -1 }
2624 };
2625
2626 static struct omap_hwmod omap44xx_mpu_hwmod = {
2627         .name           = "mpu",
2628         .class          = &omap44xx_mpu_hwmod_class,
2629         .clkdm_name     = "mpuss_clkdm",
2630         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2631         .mpu_irqs       = omap44xx_mpu_irqs,
2632         .main_clk       = "dpll_mpu_m2_ck",
2633         .prcm = {
2634                 .omap4 = {
2635                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2636                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2637                 },
2638         },
2639 };
2640
2641 /*
2642  * 'ocmc_ram' class
2643  * top-level core on-chip ram
2644  */
2645
2646 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2647         .name   = "ocmc_ram",
2648 };
2649
2650 /* ocmc_ram */
2651 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2652         .name           = "ocmc_ram",
2653         .class          = &omap44xx_ocmc_ram_hwmod_class,
2654         .clkdm_name     = "l3_2_clkdm",
2655         .prcm = {
2656                 .omap4 = {
2657                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2658                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2659                 },
2660         },
2661 };
2662
2663 /*
2664  * 'ocp2scp' class
2665  * bridge to transform ocp interface protocol to scp (serial control port)
2666  * protocol
2667  */
2668
2669 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2670         .rev_offs       = 0x0000,
2671         .sysc_offs      = 0x0010,
2672         .syss_offs      = 0x0014,
2673         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2674                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2675         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2676         .sysc_fields    = &omap_hwmod_sysc_type1,
2677 };
2678
2679 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2680         .name   = "ocp2scp",
2681         .sysc   = &omap44xx_ocp2scp_sysc,
2682 };
2683
2684 /* ocp2scp_usb_phy */
2685 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2686         .name           = "ocp2scp_usb_phy",
2687         .class          = &omap44xx_ocp2scp_hwmod_class,
2688         .clkdm_name     = "l3_init_clkdm",
2689         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2690         .prcm = {
2691                 .omap4 = {
2692                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2693                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2694                         .modulemode   = MODULEMODE_HWCTRL,
2695                 },
2696         },
2697 };
2698
2699 /*
2700  * 'prcm' class
2701  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2702  * + clock manager 1 (in always on power domain) + local prm in mpu
2703  */
2704
2705 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2706         .name   = "prcm",
2707 };
2708
2709 /* prcm_mpu */
2710 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2711         .name           = "prcm_mpu",
2712         .class          = &omap44xx_prcm_hwmod_class,
2713         .clkdm_name     = "l4_wkup_clkdm",
2714         .flags          = HWMOD_NO_IDLEST,
2715         .prcm = {
2716                 .omap4 = {
2717                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2718                 },
2719         },
2720 };
2721
2722 /* cm_core_aon */
2723 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2724         .name           = "cm_core_aon",
2725         .class          = &omap44xx_prcm_hwmod_class,
2726         .flags          = HWMOD_NO_IDLEST,
2727         .prcm = {
2728                 .omap4 = {
2729                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2730                 },
2731         },
2732 };
2733
2734 /* cm_core */
2735 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2736         .name           = "cm_core",
2737         .class          = &omap44xx_prcm_hwmod_class,
2738         .flags          = HWMOD_NO_IDLEST,
2739         .prcm = {
2740                 .omap4 = {
2741                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2742                 },
2743         },
2744 };
2745
2746 /* prm */
2747 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2748         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2749         { .irq = -1 }
2750 };
2751
2752 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2753         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2754         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2755 };
2756
2757 static struct omap_hwmod omap44xx_prm_hwmod = {
2758         .name           = "prm",
2759         .class          = &omap44xx_prcm_hwmod_class,
2760         .mpu_irqs       = omap44xx_prm_irqs,
2761         .rst_lines      = omap44xx_prm_resets,
2762         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2763 };
2764
2765 /*
2766  * 'scrm' class
2767  * system clock and reset manager
2768  */
2769
2770 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2771         .name   = "scrm",
2772 };
2773
2774 /* scrm */
2775 static struct omap_hwmod omap44xx_scrm_hwmod = {
2776         .name           = "scrm",
2777         .class          = &omap44xx_scrm_hwmod_class,
2778         .clkdm_name     = "l4_wkup_clkdm",
2779         .prcm = {
2780                 .omap4 = {
2781                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2782                 },
2783         },
2784 };
2785
2786 /*
2787  * 'sl2if' class
2788  * shared level 2 memory interface
2789  */
2790
2791 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2792         .name   = "sl2if",
2793 };
2794
2795 /* sl2if */
2796 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2797         .name           = "sl2if",
2798         .class          = &omap44xx_sl2if_hwmod_class,
2799         .clkdm_name     = "ivahd_clkdm",
2800         .prcm = {
2801                 .omap4 = {
2802                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2803                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2804                         .modulemode   = MODULEMODE_HWCTRL,
2805                 },
2806         },
2807 };
2808
2809 /*
2810  * 'slimbus' class
2811  * bidirectional, multi-drop, multi-channel two-line serial interface between
2812  * the device and external components
2813  */
2814
2815 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2816         .rev_offs       = 0x0000,
2817         .sysc_offs      = 0x0010,
2818         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2819                            SYSC_HAS_SOFTRESET),
2820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2821                            SIDLE_SMART_WKUP),
2822         .sysc_fields    = &omap_hwmod_sysc_type2,
2823 };
2824
2825 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2826         .name   = "slimbus",
2827         .sysc   = &omap44xx_slimbus_sysc,
2828 };
2829
2830 /* slimbus1 */
2831 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2832         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2833         { .irq = -1 }
2834 };
2835
2836 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2837         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2838         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2839         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2840         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2841         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2842         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2843         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2844         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2845         { .dma_req = -1 }
2846 };
2847
2848 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2849         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2850         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2851         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2852         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2853 };
2854
2855 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2856         .name           = "slimbus1",
2857         .class          = &omap44xx_slimbus_hwmod_class,
2858         .clkdm_name     = "abe_clkdm",
2859         .mpu_irqs       = omap44xx_slimbus1_irqs,
2860         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2861         .prcm = {
2862                 .omap4 = {
2863                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2864                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2865                         .modulemode   = MODULEMODE_SWCTRL,
2866                 },
2867         },
2868         .opt_clks       = slimbus1_opt_clks,
2869         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2870 };
2871
2872 /* slimbus2 */
2873 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2874         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2875         { .irq = -1 }
2876 };
2877
2878 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2879         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2880         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2881         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2882         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2883         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2884         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2885         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2886         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2887         { .dma_req = -1 }
2888 };
2889
2890 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2891         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2892         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2893         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2894 };
2895
2896 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2897         .name           = "slimbus2",
2898         .class          = &omap44xx_slimbus_hwmod_class,
2899         .clkdm_name     = "l4_per_clkdm",
2900         .mpu_irqs       = omap44xx_slimbus2_irqs,
2901         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2902         .prcm = {
2903                 .omap4 = {
2904                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2905                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2906                         .modulemode   = MODULEMODE_SWCTRL,
2907                 },
2908         },
2909         .opt_clks       = slimbus2_opt_clks,
2910         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2911 };
2912
2913 /*
2914  * 'smartreflex' class
2915  * smartreflex module (monitor silicon performance and outputs a measure of
2916  * performance error)
2917  */
2918
2919 /* The IP is not compliant to type1 / type2 scheme */
2920 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2921         .sidle_shift    = 24,
2922         .enwkup_shift   = 26,
2923 };
2924
2925 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2926         .sysc_offs      = 0x0038,
2927         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2929                            SIDLE_SMART_WKUP),
2930         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2931 };
2932
2933 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2934         .name   = "smartreflex",
2935         .sysc   = &omap44xx_smartreflex_sysc,
2936         .rev    = 2,
2937 };
2938
2939 /* smartreflex_core */
2940 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2941         .sensor_voltdm_name   = "core",
2942 };
2943
2944 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2945         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2946         { .irq = -1 }
2947 };
2948
2949 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2950         .name           = "smartreflex_core",
2951         .class          = &omap44xx_smartreflex_hwmod_class,
2952         .clkdm_name     = "l4_ao_clkdm",
2953         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2954
2955         .main_clk       = "smartreflex_core_fck",
2956         .prcm = {
2957                 .omap4 = {
2958                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2959                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2960                         .modulemode   = MODULEMODE_SWCTRL,
2961                 },
2962         },
2963         .dev_attr       = &smartreflex_core_dev_attr,
2964 };
2965
2966 /* smartreflex_iva */
2967 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2968         .sensor_voltdm_name     = "iva",
2969 };
2970
2971 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2972         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2973         { .irq = -1 }
2974 };
2975
2976 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2977         .name           = "smartreflex_iva",
2978         .class          = &omap44xx_smartreflex_hwmod_class,
2979         .clkdm_name     = "l4_ao_clkdm",
2980         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
2981         .main_clk       = "smartreflex_iva_fck",
2982         .prcm = {
2983                 .omap4 = {
2984                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2985                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2986                         .modulemode   = MODULEMODE_SWCTRL,
2987                 },
2988         },
2989         .dev_attr       = &smartreflex_iva_dev_attr,
2990 };
2991
2992 /* smartreflex_mpu */
2993 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2994         .sensor_voltdm_name     = "mpu",
2995 };
2996
2997 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2998         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
2999         { .irq = -1 }
3000 };
3001
3002 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3003         .name           = "smartreflex_mpu",
3004         .class          = &omap44xx_smartreflex_hwmod_class,
3005         .clkdm_name     = "l4_ao_clkdm",
3006         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3007         .main_clk       = "smartreflex_mpu_fck",
3008         .prcm = {
3009                 .omap4 = {
3010                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3011                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3012                         .modulemode   = MODULEMODE_SWCTRL,
3013                 },
3014         },
3015         .dev_attr       = &smartreflex_mpu_dev_attr,
3016 };
3017
3018 /*
3019  * 'spinlock' class
3020  * spinlock provides hardware assistance for synchronizing the processes
3021  * running on multiple processors
3022  */
3023
3024 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3025         .rev_offs       = 0x0000,
3026         .sysc_offs      = 0x0010,
3027         .syss_offs      = 0x0014,
3028         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3029                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3030                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3031         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3032                            SIDLE_SMART_WKUP),
3033         .sysc_fields    = &omap_hwmod_sysc_type1,
3034 };
3035
3036 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3037         .name   = "spinlock",
3038         .sysc   = &omap44xx_spinlock_sysc,
3039 };
3040
3041 /* spinlock */
3042 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3043         .name           = "spinlock",
3044         .class          = &omap44xx_spinlock_hwmod_class,
3045         .clkdm_name     = "l4_cfg_clkdm",
3046         .prcm = {
3047                 .omap4 = {
3048                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3049                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3050                 },
3051         },
3052 };
3053
3054 /*
3055  * 'timer' class
3056  * general purpose timer module with accurate 1ms tick
3057  * This class contains several variants: ['timer_1ms', 'timer']
3058  */
3059
3060 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3061         .rev_offs       = 0x0000,
3062         .sysc_offs      = 0x0010,
3063         .syss_offs      = 0x0014,
3064         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3065                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3066                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3067                            SYSS_HAS_RESET_STATUS),
3068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3069         .sysc_fields    = &omap_hwmod_sysc_type1,
3070 };
3071
3072 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3073         .name   = "timer",
3074         .sysc   = &omap44xx_timer_1ms_sysc,
3075 };
3076
3077 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3078         .rev_offs       = 0x0000,
3079         .sysc_offs      = 0x0010,
3080         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3081                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3082         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3083                            SIDLE_SMART_WKUP),
3084         .sysc_fields    = &omap_hwmod_sysc_type2,
3085 };
3086
3087 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3088         .name   = "timer",
3089         .sysc   = &omap44xx_timer_sysc,
3090 };
3091
3092 /* always-on timers dev attribute */
3093 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3094         .timer_capability       = OMAP_TIMER_ALWON,
3095 };
3096
3097 /* pwm timers dev attribute */
3098 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3099         .timer_capability       = OMAP_TIMER_HAS_PWM,
3100 };
3101
3102 /* timers with DSP interrupt dev attribute */
3103 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3104         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3105 };
3106
3107 /* pwm timers with DSP interrupt dev attribute */
3108 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3109         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3110 };
3111
3112 /* timer1 */
3113 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3114         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3115         { .irq = -1 }
3116 };
3117
3118 static struct omap_hwmod omap44xx_timer1_hwmod = {
3119         .name           = "timer1",
3120         .class          = &omap44xx_timer_1ms_hwmod_class,
3121         .clkdm_name     = "l4_wkup_clkdm",
3122         .mpu_irqs       = omap44xx_timer1_irqs,
3123         .main_clk       = "timer1_fck",
3124         .prcm = {
3125                 .omap4 = {
3126                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3127                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3128                         .modulemode   = MODULEMODE_SWCTRL,
3129                 },
3130         },
3131         .dev_attr       = &capability_alwon_dev_attr,
3132 };
3133
3134 /* timer2 */
3135 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3136         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3137         { .irq = -1 }
3138 };
3139
3140 static struct omap_hwmod omap44xx_timer2_hwmod = {
3141         .name           = "timer2",
3142         .class          = &omap44xx_timer_1ms_hwmod_class,
3143         .clkdm_name     = "l4_per_clkdm",
3144         .mpu_irqs       = omap44xx_timer2_irqs,
3145         .main_clk       = "timer2_fck",
3146         .prcm = {
3147                 .omap4 = {
3148                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3149                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3150                         .modulemode   = MODULEMODE_SWCTRL,
3151                 },
3152         },
3153 };
3154
3155 /* timer3 */
3156 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3157         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3158         { .irq = -1 }
3159 };
3160
3161 static struct omap_hwmod omap44xx_timer3_hwmod = {
3162         .name           = "timer3",
3163         .class          = &omap44xx_timer_hwmod_class,
3164         .clkdm_name     = "l4_per_clkdm",
3165         .mpu_irqs       = omap44xx_timer3_irqs,
3166         .main_clk       = "timer3_fck",
3167         .prcm = {
3168                 .omap4 = {
3169                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3170                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3171                         .modulemode   = MODULEMODE_SWCTRL,
3172                 },
3173         },
3174 };
3175
3176 /* timer4 */
3177 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3178         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3179         { .irq = -1 }
3180 };
3181
3182 static struct omap_hwmod omap44xx_timer4_hwmod = {
3183         .name           = "timer4",
3184         .class          = &omap44xx_timer_hwmod_class,
3185         .clkdm_name     = "l4_per_clkdm",
3186         .mpu_irqs       = omap44xx_timer4_irqs,
3187         .main_clk       = "timer4_fck",
3188         .prcm = {
3189                 .omap4 = {
3190                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3191                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3192                         .modulemode   = MODULEMODE_SWCTRL,
3193                 },
3194         },
3195 };
3196
3197 /* timer5 */
3198 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3199         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3200         { .irq = -1 }
3201 };
3202
3203 static struct omap_hwmod omap44xx_timer5_hwmod = {
3204         .name           = "timer5",
3205         .class          = &omap44xx_timer_hwmod_class,
3206         .clkdm_name     = "abe_clkdm",
3207         .mpu_irqs       = omap44xx_timer5_irqs,
3208         .main_clk       = "timer5_fck",
3209         .prcm = {
3210                 .omap4 = {
3211                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3212                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3213                         .modulemode   = MODULEMODE_SWCTRL,
3214                 },
3215         },
3216         .dev_attr       = &capability_dsp_dev_attr,
3217 };
3218
3219 /* timer6 */
3220 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3221         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3222         { .irq = -1 }
3223 };
3224
3225 static struct omap_hwmod omap44xx_timer6_hwmod = {
3226         .name           = "timer6",
3227         .class          = &omap44xx_timer_hwmod_class,
3228         .clkdm_name     = "abe_clkdm",
3229         .mpu_irqs       = omap44xx_timer6_irqs,
3230
3231         .main_clk       = "timer6_fck",
3232         .prcm = {
3233                 .omap4 = {
3234                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3235                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3236                         .modulemode   = MODULEMODE_SWCTRL,
3237                 },
3238         },
3239         .dev_attr       = &capability_dsp_dev_attr,
3240 };
3241
3242 /* timer7 */
3243 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3244         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3245         { .irq = -1 }
3246 };
3247
3248 static struct omap_hwmod omap44xx_timer7_hwmod = {
3249         .name           = "timer7",
3250         .class          = &omap44xx_timer_hwmod_class,
3251         .clkdm_name     = "abe_clkdm",
3252         .mpu_irqs       = omap44xx_timer7_irqs,
3253         .main_clk       = "timer7_fck",
3254         .prcm = {
3255                 .omap4 = {
3256                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3257                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3258                         .modulemode   = MODULEMODE_SWCTRL,
3259                 },
3260         },
3261         .dev_attr       = &capability_dsp_dev_attr,
3262 };
3263
3264 /* timer8 */
3265 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3266         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3267         { .irq = -1 }
3268 };
3269
3270 static struct omap_hwmod omap44xx_timer8_hwmod = {
3271         .name           = "timer8",
3272         .class          = &omap44xx_timer_hwmod_class,
3273         .clkdm_name     = "abe_clkdm",
3274         .mpu_irqs       = omap44xx_timer8_irqs,
3275         .main_clk       = "timer8_fck",
3276         .prcm = {
3277                 .omap4 = {
3278                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3279                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3280                         .modulemode   = MODULEMODE_SWCTRL,
3281                 },
3282         },
3283         .dev_attr       = &capability_dsp_pwm_dev_attr,
3284 };
3285
3286 /* timer9 */
3287 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3288         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3289         { .irq = -1 }
3290 };
3291
3292 static struct omap_hwmod omap44xx_timer9_hwmod = {
3293         .name           = "timer9",
3294         .class          = &omap44xx_timer_hwmod_class,
3295         .clkdm_name     = "l4_per_clkdm",
3296         .mpu_irqs       = omap44xx_timer9_irqs,
3297         .main_clk       = "timer9_fck",
3298         .prcm = {
3299                 .omap4 = {
3300                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3301                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3302                         .modulemode   = MODULEMODE_SWCTRL,
3303                 },
3304         },
3305         .dev_attr       = &capability_pwm_dev_attr,
3306 };
3307
3308 /* timer10 */
3309 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3310         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3311         { .irq = -1 }
3312 };
3313
3314 static struct omap_hwmod omap44xx_timer10_hwmod = {
3315         .name           = "timer10",
3316         .class          = &omap44xx_timer_1ms_hwmod_class,
3317         .clkdm_name     = "l4_per_clkdm",
3318         .mpu_irqs       = omap44xx_timer10_irqs,
3319         .main_clk       = "timer10_fck",
3320         .prcm = {
3321                 .omap4 = {
3322                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3323                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3324                         .modulemode   = MODULEMODE_SWCTRL,
3325                 },
3326         },
3327         .dev_attr       = &capability_pwm_dev_attr,
3328 };
3329
3330 /* timer11 */
3331 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3332         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3333         { .irq = -1 }
3334 };
3335
3336 static struct omap_hwmod omap44xx_timer11_hwmod = {
3337         .name           = "timer11",
3338         .class          = &omap44xx_timer_hwmod_class,
3339         .clkdm_name     = "l4_per_clkdm",
3340         .mpu_irqs       = omap44xx_timer11_irqs,
3341         .main_clk       = "timer11_fck",
3342         .prcm = {
3343                 .omap4 = {
3344                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3345                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3346                         .modulemode   = MODULEMODE_SWCTRL,
3347                 },
3348         },
3349         .dev_attr       = &capability_pwm_dev_attr,
3350 };
3351
3352 /*
3353  * 'uart' class
3354  * universal asynchronous receiver/transmitter (uart)
3355  */
3356
3357 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3358         .rev_offs       = 0x0050,
3359         .sysc_offs      = 0x0054,
3360         .syss_offs      = 0x0058,
3361         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3362                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3363                            SYSS_HAS_RESET_STATUS),
3364         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3365                            SIDLE_SMART_WKUP),
3366         .sysc_fields    = &omap_hwmod_sysc_type1,
3367 };
3368
3369 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3370         .name   = "uart",
3371         .sysc   = &omap44xx_uart_sysc,
3372 };
3373
3374 /* uart1 */
3375 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3376         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3377         { .irq = -1 }
3378 };
3379
3380 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3381         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3382         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3383         { .dma_req = -1 }
3384 };
3385
3386 static struct omap_hwmod omap44xx_uart1_hwmod = {
3387         .name           = "uart1",
3388         .class          = &omap44xx_uart_hwmod_class,
3389         .clkdm_name     = "l4_per_clkdm",
3390         .mpu_irqs       = omap44xx_uart1_irqs,
3391         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3392         .main_clk       = "uart1_fck",
3393         .prcm = {
3394                 .omap4 = {
3395                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3396                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3397                         .modulemode   = MODULEMODE_SWCTRL,
3398                 },
3399         },
3400 };
3401
3402 /* uart2 */
3403 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3404         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3405         { .irq = -1 }
3406 };
3407
3408 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3409         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3410         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3411         { .dma_req = -1 }
3412 };
3413
3414 static struct omap_hwmod omap44xx_uart2_hwmod = {
3415         .name           = "uart2",
3416         .class          = &omap44xx_uart_hwmod_class,
3417         .clkdm_name     = "l4_per_clkdm",
3418         .mpu_irqs       = omap44xx_uart2_irqs,
3419         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3420         .main_clk       = "uart2_fck",
3421         .prcm = {
3422                 .omap4 = {
3423                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3424                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3425                         .modulemode   = MODULEMODE_SWCTRL,
3426                 },
3427         },
3428 };
3429
3430 /* uart3 */
3431 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3432         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3433         { .irq = -1 }
3434 };
3435
3436 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3437         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3438         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3439         { .dma_req = -1 }
3440 };
3441
3442 static struct omap_hwmod omap44xx_uart3_hwmod = {
3443         .name           = "uart3",
3444         .class          = &omap44xx_uart_hwmod_class,
3445         .clkdm_name     = "l4_per_clkdm",
3446         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3447         .mpu_irqs       = omap44xx_uart3_irqs,
3448         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3449         .main_clk       = "uart3_fck",
3450         .prcm = {
3451                 .omap4 = {
3452                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3453                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3454                         .modulemode   = MODULEMODE_SWCTRL,
3455                 },
3456         },
3457 };
3458
3459 /* uart4 */
3460 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3461         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3462         { .irq = -1 }
3463 };
3464
3465 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3466         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3467         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3468         { .dma_req = -1 }
3469 };
3470
3471 static struct omap_hwmod omap44xx_uart4_hwmod = {
3472         .name           = "uart4",
3473         .class          = &omap44xx_uart_hwmod_class,
3474         .clkdm_name     = "l4_per_clkdm",
3475         .mpu_irqs       = omap44xx_uart4_irqs,
3476         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3477         .main_clk       = "uart4_fck",
3478         .prcm = {
3479                 .omap4 = {
3480                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3481                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3482                         .modulemode   = MODULEMODE_SWCTRL,
3483                 },
3484         },
3485 };
3486
3487 /*
3488  * 'usb_host_fs' class
3489  * full-speed usb host controller
3490  */
3491
3492 /* The IP is not compliant to type1 / type2 scheme */
3493 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3494         .midle_shift    = 4,
3495         .sidle_shift    = 2,
3496         .srst_shift     = 1,
3497 };
3498
3499 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3500         .rev_offs       = 0x0000,
3501         .sysc_offs      = 0x0210,
3502         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3503                            SYSC_HAS_SOFTRESET),
3504         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3505                            SIDLE_SMART_WKUP),
3506         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3507 };
3508
3509 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3510         .name   = "usb_host_fs",
3511         .sysc   = &omap44xx_usb_host_fs_sysc,
3512 };
3513
3514 /* usb_host_fs */
3515 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3516         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3517         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3518         { .irq = -1 }
3519 };
3520
3521 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3522         .name           = "usb_host_fs",
3523         .class          = &omap44xx_usb_host_fs_hwmod_class,
3524         .clkdm_name     = "l3_init_clkdm",
3525         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3526         .main_clk       = "usb_host_fs_fck",
3527         .prcm = {
3528                 .omap4 = {
3529                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3530                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3531                         .modulemode   = MODULEMODE_SWCTRL,
3532                 },
3533         },
3534 };
3535
3536 /*
3537  * 'usb_host_hs' class
3538  * high-speed multi-port usb host controller
3539  */
3540
3541 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3542         .rev_offs       = 0x0000,
3543         .sysc_offs      = 0x0010,
3544         .syss_offs      = 0x0014,
3545         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3546                            SYSC_HAS_SOFTRESET),
3547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3548                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3549                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3550         .sysc_fields    = &omap_hwmod_sysc_type2,
3551 };
3552
3553 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3554         .name   = "usb_host_hs",
3555         .sysc   = &omap44xx_usb_host_hs_sysc,
3556 };
3557
3558 /* usb_host_hs */
3559 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3560         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3561         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3562         { .irq = -1 }
3563 };
3564
3565 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3566         .name           = "usb_host_hs",
3567         .class          = &omap44xx_usb_host_hs_hwmod_class,
3568         .clkdm_name     = "l3_init_clkdm",
3569         .main_clk       = "usb_host_hs_fck",
3570         .prcm = {
3571                 .omap4 = {
3572                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3573                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3574                         .modulemode   = MODULEMODE_SWCTRL,
3575                 },
3576         },
3577         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3578
3579         /*
3580          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3581          * id: i660
3582          *
3583          * Description:
3584          * In the following configuration :
3585          * - USBHOST module is set to smart-idle mode
3586          * - PRCM asserts idle_req to the USBHOST module ( This typically
3587          *   happens when the system is going to a low power mode : all ports
3588          *   have been suspended, the master part of the USBHOST module has
3589          *   entered the standby state, and SW has cut the functional clocks)
3590          * - an USBHOST interrupt occurs before the module is able to answer
3591          *   idle_ack, typically a remote wakeup IRQ.
3592          * Then the USB HOST module will enter a deadlock situation where it
3593          * is no more accessible nor functional.
3594          *
3595          * Workaround:
3596          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3597          */
3598
3599         /*
3600          * Errata: USB host EHCI may stall when entering smart-standby mode
3601          * Id: i571
3602          *
3603          * Description:
3604          * When the USBHOST module is set to smart-standby mode, and when it is
3605          * ready to enter the standby state (i.e. all ports are suspended and
3606          * all attached devices are in suspend mode), then it can wrongly assert
3607          * the Mstandby signal too early while there are still some residual OCP
3608          * transactions ongoing. If this condition occurs, the internal state
3609          * machine may go to an undefined state and the USB link may be stuck
3610          * upon the next resume.
3611          *
3612          * Workaround:
3613          * Don't use smart standby; use only force standby,
3614          * hence HWMOD_SWSUP_MSTANDBY
3615          */
3616
3617         /*
3618          * During system boot; If the hwmod framework resets the module
3619          * the module will have smart idle settings; which can lead to deadlock
3620          * (above Errata Id:i660); so, dont reset the module during boot;
3621          * Use HWMOD_INIT_NO_RESET.
3622          */
3623
3624         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3625                           HWMOD_INIT_NO_RESET,
3626 };
3627
3628 /*
3629  * 'usb_otg_hs' class
3630  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3631  */
3632
3633 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3634         .rev_offs       = 0x0400,
3635         .sysc_offs      = 0x0404,
3636         .syss_offs      = 0x0408,
3637         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3638                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3639                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3640         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3641                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3642                            MSTANDBY_SMART),
3643         .sysc_fields    = &omap_hwmod_sysc_type1,
3644 };
3645
3646 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3647         .name   = "usb_otg_hs",
3648         .sysc   = &omap44xx_usb_otg_hs_sysc,
3649 };
3650
3651 /* usb_otg_hs */
3652 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3653         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3654         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3655         { .irq = -1 }
3656 };
3657
3658 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3659         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3660 };
3661
3662 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3663         .name           = "usb_otg_hs",
3664         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3665         .clkdm_name     = "l3_init_clkdm",
3666         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3667         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3668         .main_clk       = "usb_otg_hs_ick",
3669         .prcm = {
3670                 .omap4 = {
3671                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3672                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3673                         .modulemode   = MODULEMODE_HWCTRL,
3674                 },
3675         },
3676         .opt_clks       = usb_otg_hs_opt_clks,
3677         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3678 };
3679
3680 /*
3681  * 'usb_tll_hs' class
3682  * usb_tll_hs module is the adapter on the usb_host_hs ports
3683  */
3684
3685 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3686         .rev_offs       = 0x0000,
3687         .sysc_offs      = 0x0010,
3688         .syss_offs      = 0x0014,
3689         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3690                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3691                            SYSC_HAS_AUTOIDLE),
3692         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3693         .sysc_fields    = &omap_hwmod_sysc_type1,
3694 };
3695
3696 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3697         .name   = "usb_tll_hs",
3698         .sysc   = &omap44xx_usb_tll_hs_sysc,
3699 };
3700
3701 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3702         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3703         { .irq = -1 }
3704 };
3705
3706 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3707         .name           = "usb_tll_hs",
3708         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3709         .clkdm_name     = "l3_init_clkdm",
3710         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3711         .main_clk       = "usb_tll_hs_ick",
3712         .prcm = {
3713                 .omap4 = {
3714                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3715                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3716                         .modulemode   = MODULEMODE_HWCTRL,
3717                 },
3718         },
3719 };
3720
3721 /*
3722  * 'wd_timer' class
3723  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3724  * overflow condition
3725  */
3726
3727 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3728         .rev_offs       = 0x0000,
3729         .sysc_offs      = 0x0010,
3730         .syss_offs      = 0x0014,
3731         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3732                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3733         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3734                            SIDLE_SMART_WKUP),
3735         .sysc_fields    = &omap_hwmod_sysc_type1,
3736 };
3737
3738 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3739         .name           = "wd_timer",
3740         .sysc           = &omap44xx_wd_timer_sysc,
3741         .pre_shutdown   = &omap2_wd_timer_disable,
3742         .reset          = &omap2_wd_timer_reset,
3743 };
3744
3745 /* wd_timer2 */
3746 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3747         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3748         { .irq = -1 }
3749 };
3750
3751 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3752         .name           = "wd_timer2",
3753         .class          = &omap44xx_wd_timer_hwmod_class,
3754         .clkdm_name     = "l4_wkup_clkdm",
3755         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3756         .main_clk       = "wd_timer2_fck",
3757         .prcm = {
3758                 .omap4 = {
3759                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3760                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3761                         .modulemode   = MODULEMODE_SWCTRL,
3762                 },
3763         },
3764 };
3765
3766 /* wd_timer3 */
3767 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3768         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3769         { .irq = -1 }
3770 };
3771
3772 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3773         .name           = "wd_timer3",
3774         .class          = &omap44xx_wd_timer_hwmod_class,
3775         .clkdm_name     = "abe_clkdm",
3776         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3777         .main_clk       = "wd_timer3_fck",
3778         .prcm = {
3779                 .omap4 = {
3780                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3781                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3782                         .modulemode   = MODULEMODE_SWCTRL,
3783                 },
3784         },
3785 };
3786
3787
3788 /*
3789  * interfaces
3790  */
3791
3792 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3793         {
3794                 .pa_start       = 0x4a204000,
3795                 .pa_end         = 0x4a2040ff,
3796                 .flags          = ADDR_TYPE_RT
3797         },
3798         { }
3799 };
3800
3801 /* c2c -> c2c_target_fw */
3802 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3803         .master         = &omap44xx_c2c_hwmod,
3804         .slave          = &omap44xx_c2c_target_fw_hwmod,
3805         .clk            = "div_core_ck",
3806         .addr           = omap44xx_c2c_target_fw_addrs,
3807         .user           = OCP_USER_MPU,
3808 };
3809
3810 /* l4_cfg -> c2c_target_fw */
3811 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3812         .master         = &omap44xx_l4_cfg_hwmod,
3813         .slave          = &omap44xx_c2c_target_fw_hwmod,
3814         .clk            = "l4_div_ck",
3815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3816 };
3817
3818 /* l3_main_1 -> dmm */
3819 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3820         .master         = &omap44xx_l3_main_1_hwmod,
3821         .slave          = &omap44xx_dmm_hwmod,
3822         .clk            = "l3_div_ck",
3823         .user           = OCP_USER_SDMA,
3824 };
3825
3826 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3827         {
3828                 .pa_start       = 0x4e000000,
3829                 .pa_end         = 0x4e0007ff,
3830                 .flags          = ADDR_TYPE_RT
3831         },
3832         { }
3833 };
3834
3835 /* mpu -> dmm */
3836 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3837         .master         = &omap44xx_mpu_hwmod,
3838         .slave          = &omap44xx_dmm_hwmod,
3839         .clk            = "l3_div_ck",
3840         .addr           = omap44xx_dmm_addrs,
3841         .user           = OCP_USER_MPU,
3842 };
3843
3844 /* c2c -> emif_fw */
3845 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3846         .master         = &omap44xx_c2c_hwmod,
3847         .slave          = &omap44xx_emif_fw_hwmod,
3848         .clk            = "div_core_ck",
3849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3850 };
3851
3852 /* dmm -> emif_fw */
3853 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3854         .master         = &omap44xx_dmm_hwmod,
3855         .slave          = &omap44xx_emif_fw_hwmod,
3856         .clk            = "l3_div_ck",
3857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3858 };
3859
3860 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3861         {
3862                 .pa_start       = 0x4a20c000,
3863                 .pa_end         = 0x4a20c0ff,
3864                 .flags          = ADDR_TYPE_RT
3865         },
3866         { }
3867 };
3868
3869 /* l4_cfg -> emif_fw */
3870 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3871         .master         = &omap44xx_l4_cfg_hwmod,
3872         .slave          = &omap44xx_emif_fw_hwmod,
3873         .clk            = "l4_div_ck",
3874         .addr           = omap44xx_emif_fw_addrs,
3875         .user           = OCP_USER_MPU,
3876 };
3877
3878 /* iva -> l3_instr */
3879 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3880         .master         = &omap44xx_iva_hwmod,
3881         .slave          = &omap44xx_l3_instr_hwmod,
3882         .clk            = "l3_div_ck",
3883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3884 };
3885
3886 /* l3_main_3 -> l3_instr */
3887 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3888         .master         = &omap44xx_l3_main_3_hwmod,
3889         .slave          = &omap44xx_l3_instr_hwmod,
3890         .clk            = "l3_div_ck",
3891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3892 };
3893
3894 /* ocp_wp_noc -> l3_instr */
3895 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3896         .master         = &omap44xx_ocp_wp_noc_hwmod,
3897         .slave          = &omap44xx_l3_instr_hwmod,
3898         .clk            = "l3_div_ck",
3899         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3900 };
3901
3902 /* dsp -> l3_main_1 */
3903 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3904         .master         = &omap44xx_dsp_hwmod,
3905         .slave          = &omap44xx_l3_main_1_hwmod,
3906         .clk            = "l3_div_ck",
3907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3908 };
3909
3910 /* dss -> l3_main_1 */
3911 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3912         .master         = &omap44xx_dss_hwmod,
3913         .slave          = &omap44xx_l3_main_1_hwmod,
3914         .clk            = "l3_div_ck",
3915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3916 };
3917
3918 /* l3_main_2 -> l3_main_1 */
3919 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3920         .master         = &omap44xx_l3_main_2_hwmod,
3921         .slave          = &omap44xx_l3_main_1_hwmod,
3922         .clk            = "l3_div_ck",
3923         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3924 };
3925
3926 /* l4_cfg -> l3_main_1 */
3927 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3928         .master         = &omap44xx_l4_cfg_hwmod,
3929         .slave          = &omap44xx_l3_main_1_hwmod,
3930         .clk            = "l4_div_ck",
3931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3932 };
3933
3934 /* mmc1 -> l3_main_1 */
3935 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3936         .master         = &omap44xx_mmc1_hwmod,
3937         .slave          = &omap44xx_l3_main_1_hwmod,
3938         .clk            = "l3_div_ck",
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* mmc2 -> l3_main_1 */
3943 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3944         .master         = &omap44xx_mmc2_hwmod,
3945         .slave          = &omap44xx_l3_main_1_hwmod,
3946         .clk            = "l3_div_ck",
3947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3948 };
3949
3950 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3951         {
3952                 .pa_start       = 0x44000000,
3953                 .pa_end         = 0x44000fff,
3954                 .flags          = ADDR_TYPE_RT
3955         },
3956         { }
3957 };
3958
3959 /* mpu -> l3_main_1 */
3960 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3961         .master         = &omap44xx_mpu_hwmod,
3962         .slave          = &omap44xx_l3_main_1_hwmod,
3963         .clk            = "l3_div_ck",
3964         .addr           = omap44xx_l3_main_1_addrs,
3965         .user           = OCP_USER_MPU,
3966 };
3967
3968 /* c2c_target_fw -> l3_main_2 */
3969 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3970         .master         = &omap44xx_c2c_target_fw_hwmod,
3971         .slave          = &omap44xx_l3_main_2_hwmod,
3972         .clk            = "l3_div_ck",
3973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3974 };
3975
3976 /* debugss -> l3_main_2 */
3977 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3978         .master         = &omap44xx_debugss_hwmod,
3979         .slave          = &omap44xx_l3_main_2_hwmod,
3980         .clk            = "dbgclk_mux_ck",
3981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3982 };
3983
3984 /* dma_system -> l3_main_2 */
3985 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3986         .master         = &omap44xx_dma_system_hwmod,
3987         .slave          = &omap44xx_l3_main_2_hwmod,
3988         .clk            = "l3_div_ck",
3989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3990 };
3991
3992 /* fdif -> l3_main_2 */
3993 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3994         .master         = &omap44xx_fdif_hwmod,
3995         .slave          = &omap44xx_l3_main_2_hwmod,
3996         .clk            = "l3_div_ck",
3997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3998 };
3999
4000 /* gpu -> l3_main_2 */
4001 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4002         .master         = &omap44xx_gpu_hwmod,
4003         .slave          = &omap44xx_l3_main_2_hwmod,
4004         .clk            = "l3_div_ck",
4005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4006 };
4007
4008 /* hsi -> l3_main_2 */
4009 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4010         .master         = &omap44xx_hsi_hwmod,
4011         .slave          = &omap44xx_l3_main_2_hwmod,
4012         .clk            = "l3_div_ck",
4013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4014 };
4015
4016 /* ipu -> l3_main_2 */
4017 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4018         .master         = &omap44xx_ipu_hwmod,
4019         .slave          = &omap44xx_l3_main_2_hwmod,
4020         .clk            = "l3_div_ck",
4021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4022 };
4023
4024 /* iss -> l3_main_2 */
4025 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4026         .master         = &omap44xx_iss_hwmod,
4027         .slave          = &omap44xx_l3_main_2_hwmod,
4028         .clk            = "l3_div_ck",
4029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4030 };
4031
4032 /* iva -> l3_main_2 */
4033 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4034         .master         = &omap44xx_iva_hwmod,
4035         .slave          = &omap44xx_l3_main_2_hwmod,
4036         .clk            = "l3_div_ck",
4037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4038 };
4039
4040 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4041         {
4042                 .pa_start       = 0x44800000,
4043                 .pa_end         = 0x44801fff,
4044                 .flags          = ADDR_TYPE_RT
4045         },
4046         { }
4047 };
4048
4049 /* l3_main_1 -> l3_main_2 */
4050 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4051         .master         = &omap44xx_l3_main_1_hwmod,
4052         .slave          = &omap44xx_l3_main_2_hwmod,
4053         .clk            = "l3_div_ck",
4054         .addr           = omap44xx_l3_main_2_addrs,
4055         .user           = OCP_USER_MPU,
4056 };
4057
4058 /* l4_cfg -> l3_main_2 */
4059 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4060         .master         = &omap44xx_l4_cfg_hwmod,
4061         .slave          = &omap44xx_l3_main_2_hwmod,
4062         .clk            = "l4_div_ck",
4063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4064 };
4065
4066 /* usb_host_fs -> l3_main_2 */
4067 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4068         .master         = &omap44xx_usb_host_fs_hwmod,
4069         .slave          = &omap44xx_l3_main_2_hwmod,
4070         .clk            = "l3_div_ck",
4071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* usb_host_hs -> l3_main_2 */
4075 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4076         .master         = &omap44xx_usb_host_hs_hwmod,
4077         .slave          = &omap44xx_l3_main_2_hwmod,
4078         .clk            = "l3_div_ck",
4079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4080 };
4081
4082 /* usb_otg_hs -> l3_main_2 */
4083 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4084         .master         = &omap44xx_usb_otg_hs_hwmod,
4085         .slave          = &omap44xx_l3_main_2_hwmod,
4086         .clk            = "l3_div_ck",
4087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4088 };
4089
4090 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4091         {
4092                 .pa_start       = 0x45000000,
4093                 .pa_end         = 0x45000fff,
4094                 .flags          = ADDR_TYPE_RT
4095         },
4096         { }
4097 };
4098
4099 /* l3_main_1 -> l3_main_3 */
4100 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4101         .master         = &omap44xx_l3_main_1_hwmod,
4102         .slave          = &omap44xx_l3_main_3_hwmod,
4103         .clk            = "l3_div_ck",
4104         .addr           = omap44xx_l3_main_3_addrs,
4105         .user           = OCP_USER_MPU,
4106 };
4107
4108 /* l3_main_2 -> l3_main_3 */
4109 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4110         .master         = &omap44xx_l3_main_2_hwmod,
4111         .slave          = &omap44xx_l3_main_3_hwmod,
4112         .clk            = "l3_div_ck",
4113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4114 };
4115
4116 /* l4_cfg -> l3_main_3 */
4117 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4118         .master         = &omap44xx_l4_cfg_hwmod,
4119         .slave          = &omap44xx_l3_main_3_hwmod,
4120         .clk            = "l4_div_ck",
4121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4122 };
4123
4124 /* aess -> l4_abe */
4125 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4126         .master         = &omap44xx_aess_hwmod,
4127         .slave          = &omap44xx_l4_abe_hwmod,
4128         .clk            = "ocp_abe_iclk",
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 /* dsp -> l4_abe */
4133 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4134         .master         = &omap44xx_dsp_hwmod,
4135         .slave          = &omap44xx_l4_abe_hwmod,
4136         .clk            = "ocp_abe_iclk",
4137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4138 };
4139
4140 /* l3_main_1 -> l4_abe */
4141 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4142         .master         = &omap44xx_l3_main_1_hwmod,
4143         .slave          = &omap44xx_l4_abe_hwmod,
4144         .clk            = "l3_div_ck",
4145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4146 };
4147
4148 /* mpu -> l4_abe */
4149 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4150         .master         = &omap44xx_mpu_hwmod,
4151         .slave          = &omap44xx_l4_abe_hwmod,
4152         .clk            = "ocp_abe_iclk",
4153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4154 };
4155
4156 /* l3_main_1 -> l4_cfg */
4157 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4158         .master         = &omap44xx_l3_main_1_hwmod,
4159         .slave          = &omap44xx_l4_cfg_hwmod,
4160         .clk            = "l3_div_ck",
4161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4162 };
4163
4164 /* l3_main_2 -> l4_per */
4165 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4166         .master         = &omap44xx_l3_main_2_hwmod,
4167         .slave          = &omap44xx_l4_per_hwmod,
4168         .clk            = "l3_div_ck",
4169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4170 };
4171
4172 /* l4_cfg -> l4_wkup */
4173 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4174         .master         = &omap44xx_l4_cfg_hwmod,
4175         .slave          = &omap44xx_l4_wkup_hwmod,
4176         .clk            = "l4_div_ck",
4177         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 /* mpu -> mpu_private */
4181 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4182         .master         = &omap44xx_mpu_hwmod,
4183         .slave          = &omap44xx_mpu_private_hwmod,
4184         .clk            = "l3_div_ck",
4185         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4186 };
4187
4188 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4189         {
4190                 .pa_start       = 0x4a102000,
4191                 .pa_end         = 0x4a10207f,
4192                 .flags          = ADDR_TYPE_RT
4193         },
4194         { }
4195 };
4196
4197 /* l4_cfg -> ocp_wp_noc */
4198 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4199         .master         = &omap44xx_l4_cfg_hwmod,
4200         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4201         .clk            = "l4_div_ck",
4202         .addr           = omap44xx_ocp_wp_noc_addrs,
4203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4204 };
4205
4206 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4207         {
4208                 .pa_start       = 0x401f1000,
4209                 .pa_end         = 0x401f13ff,
4210                 .flags          = ADDR_TYPE_RT
4211         },
4212         { }
4213 };
4214
4215 /* l4_abe -> aess */
4216 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4217         .master         = &omap44xx_l4_abe_hwmod,
4218         .slave          = &omap44xx_aess_hwmod,
4219         .clk            = "ocp_abe_iclk",
4220         .addr           = omap44xx_aess_addrs,
4221         .user           = OCP_USER_MPU,
4222 };
4223
4224 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4225         {
4226                 .pa_start       = 0x490f1000,
4227                 .pa_end         = 0x490f13ff,
4228                 .flags          = ADDR_TYPE_RT
4229         },
4230         { }
4231 };
4232
4233 /* l4_abe -> aess (dma) */
4234 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4235         .master         = &omap44xx_l4_abe_hwmod,
4236         .slave          = &omap44xx_aess_hwmod,
4237         .clk            = "ocp_abe_iclk",
4238         .addr           = omap44xx_aess_dma_addrs,
4239         .user           = OCP_USER_SDMA,
4240 };
4241
4242 /* l3_main_2 -> c2c */
4243 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4244         .master         = &omap44xx_l3_main_2_hwmod,
4245         .slave          = &omap44xx_c2c_hwmod,
4246         .clk            = "l3_div_ck",
4247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4248 };
4249
4250 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4251         {
4252                 .pa_start       = 0x4a304000,
4253                 .pa_end         = 0x4a30401f,
4254                 .flags          = ADDR_TYPE_RT
4255         },
4256         { }
4257 };
4258
4259 /* l4_wkup -> counter_32k */
4260 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4261         .master         = &omap44xx_l4_wkup_hwmod,
4262         .slave          = &omap44xx_counter_32k_hwmod,
4263         .clk            = "l4_wkup_clk_mux_ck",
4264         .addr           = omap44xx_counter_32k_addrs,
4265         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4266 };
4267
4268 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4269         {
4270                 .pa_start       = 0x4a002000,
4271                 .pa_end         = 0x4a0027ff,
4272                 .flags          = ADDR_TYPE_RT
4273         },
4274         { }
4275 };
4276
4277 /* l4_cfg -> ctrl_module_core */
4278 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4279         .master         = &omap44xx_l4_cfg_hwmod,
4280         .slave          = &omap44xx_ctrl_module_core_hwmod,
4281         .clk            = "l4_div_ck",
4282         .addr           = omap44xx_ctrl_module_core_addrs,
4283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4284 };
4285
4286 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4287         {
4288                 .pa_start       = 0x4a100000,
4289                 .pa_end         = 0x4a1007ff,
4290                 .flags          = ADDR_TYPE_RT
4291         },
4292         { }
4293 };
4294
4295 /* l4_cfg -> ctrl_module_pad_core */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4297         .master         = &omap44xx_l4_cfg_hwmod,
4298         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4299         .clk            = "l4_div_ck",
4300         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4302 };
4303
4304 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4305         {
4306                 .pa_start       = 0x4a30c000,
4307                 .pa_end         = 0x4a30c7ff,
4308                 .flags          = ADDR_TYPE_RT
4309         },
4310         { }
4311 };
4312
4313 /* l4_wkup -> ctrl_module_wkup */
4314 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4315         .master         = &omap44xx_l4_wkup_hwmod,
4316         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4317         .clk            = "l4_wkup_clk_mux_ck",
4318         .addr           = omap44xx_ctrl_module_wkup_addrs,
4319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4320 };
4321
4322 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4323         {
4324                 .pa_start       = 0x4a31e000,
4325                 .pa_end         = 0x4a31e7ff,
4326                 .flags          = ADDR_TYPE_RT
4327         },
4328         { }
4329 };
4330
4331 /* l4_wkup -> ctrl_module_pad_wkup */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4333         .master         = &omap44xx_l4_wkup_hwmod,
4334         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4335         .clk            = "l4_wkup_clk_mux_ck",
4336         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4338 };
4339
4340 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4341         {
4342                 .pa_start       = 0x54160000,
4343                 .pa_end         = 0x54167fff,
4344                 .flags          = ADDR_TYPE_RT
4345         },
4346         { }
4347 };
4348
4349 /* l3_instr -> debugss */
4350 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4351         .master         = &omap44xx_l3_instr_hwmod,
4352         .slave          = &omap44xx_debugss_hwmod,
4353         .clk            = "l3_div_ck",
4354         .addr           = omap44xx_debugss_addrs,
4355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4356 };
4357
4358 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4359         {
4360                 .pa_start       = 0x4a056000,
4361                 .pa_end         = 0x4a056fff,
4362                 .flags          = ADDR_TYPE_RT
4363         },
4364         { }
4365 };
4366
4367 /* l4_cfg -> dma_system */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4369         .master         = &omap44xx_l4_cfg_hwmod,
4370         .slave          = &omap44xx_dma_system_hwmod,
4371         .clk            = "l4_div_ck",
4372         .addr           = omap44xx_dma_system_addrs,
4373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4374 };
4375
4376 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4377         {
4378                 .name           = "mpu",
4379                 .pa_start       = 0x4012e000,
4380                 .pa_end         = 0x4012e07f,
4381                 .flags          = ADDR_TYPE_RT
4382         },
4383         { }
4384 };
4385
4386 /* l4_abe -> dmic */
4387 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4388         .master         = &omap44xx_l4_abe_hwmod,
4389         .slave          = &omap44xx_dmic_hwmod,
4390         .clk            = "ocp_abe_iclk",
4391         .addr           = omap44xx_dmic_addrs,
4392         .user           = OCP_USER_MPU,
4393 };
4394
4395 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4396         {
4397                 .name           = "dma",
4398                 .pa_start       = 0x4902e000,
4399                 .pa_end         = 0x4902e07f,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_abe -> dmic (dma) */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4407         .master         = &omap44xx_l4_abe_hwmod,
4408         .slave          = &omap44xx_dmic_hwmod,
4409         .clk            = "ocp_abe_iclk",
4410         .addr           = omap44xx_dmic_dma_addrs,
4411         .user           = OCP_USER_SDMA,
4412 };
4413
4414 /* dsp -> iva */
4415 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4416         .master         = &omap44xx_dsp_hwmod,
4417         .slave          = &omap44xx_iva_hwmod,
4418         .clk            = "dpll_iva_m5x2_ck",
4419         .user           = OCP_USER_DSP,
4420 };
4421
4422 /* dsp -> sl2if */
4423 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4424         .master         = &omap44xx_dsp_hwmod,
4425         .slave          = &omap44xx_sl2if_hwmod,
4426         .clk            = "dpll_iva_m5x2_ck",
4427         .user           = OCP_USER_DSP,
4428 };
4429
4430 /* l4_cfg -> dsp */
4431 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4432         .master         = &omap44xx_l4_cfg_hwmod,
4433         .slave          = &omap44xx_dsp_hwmod,
4434         .clk            = "l4_div_ck",
4435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4436 };
4437
4438 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4439         {
4440                 .pa_start       = 0x58000000,
4441                 .pa_end         = 0x5800007f,
4442                 .flags          = ADDR_TYPE_RT
4443         },
4444         { }
4445 };
4446
4447 /* l3_main_2 -> dss */
4448 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4449         .master         = &omap44xx_l3_main_2_hwmod,
4450         .slave          = &omap44xx_dss_hwmod,
4451         .clk            = "dss_fck",
4452         .addr           = omap44xx_dss_dma_addrs,
4453         .user           = OCP_USER_SDMA,
4454 };
4455
4456 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4457         {
4458                 .pa_start       = 0x48040000,
4459                 .pa_end         = 0x4804007f,
4460                 .flags          = ADDR_TYPE_RT
4461         },
4462         { }
4463 };
4464
4465 /* l4_per -> dss */
4466 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4467         .master         = &omap44xx_l4_per_hwmod,
4468         .slave          = &omap44xx_dss_hwmod,
4469         .clk            = "l4_div_ck",
4470         .addr           = omap44xx_dss_addrs,
4471         .user           = OCP_USER_MPU,
4472 };
4473
4474 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4475         {
4476                 .pa_start       = 0x58001000,
4477                 .pa_end         = 0x58001fff,
4478                 .flags          = ADDR_TYPE_RT
4479         },
4480         { }
4481 };
4482
4483 /* l3_main_2 -> dss_dispc */
4484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4485         .master         = &omap44xx_l3_main_2_hwmod,
4486         .slave          = &omap44xx_dss_dispc_hwmod,
4487         .clk            = "dss_fck",
4488         .addr           = omap44xx_dss_dispc_dma_addrs,
4489         .user           = OCP_USER_SDMA,
4490 };
4491
4492 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4493         {
4494                 .pa_start       = 0x48041000,
4495                 .pa_end         = 0x48041fff,
4496                 .flags          = ADDR_TYPE_RT
4497         },
4498         { }
4499 };
4500
4501 /* l4_per -> dss_dispc */
4502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4503         .master         = &omap44xx_l4_per_hwmod,
4504         .slave          = &omap44xx_dss_dispc_hwmod,
4505         .clk            = "l4_div_ck",
4506         .addr           = omap44xx_dss_dispc_addrs,
4507         .user           = OCP_USER_MPU,
4508 };
4509
4510 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4511         {
4512                 .pa_start       = 0x58004000,
4513                 .pa_end         = 0x580041ff,
4514                 .flags          = ADDR_TYPE_RT
4515         },
4516         { }
4517 };
4518
4519 /* l3_main_2 -> dss_dsi1 */
4520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4521         .master         = &omap44xx_l3_main_2_hwmod,
4522         .slave          = &omap44xx_dss_dsi1_hwmod,
4523         .clk            = "dss_fck",
4524         .addr           = omap44xx_dss_dsi1_dma_addrs,
4525         .user           = OCP_USER_SDMA,
4526 };
4527
4528 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4529         {
4530                 .pa_start       = 0x48044000,
4531                 .pa_end         = 0x480441ff,
4532                 .flags          = ADDR_TYPE_RT
4533         },
4534         { }
4535 };
4536
4537 /* l4_per -> dss_dsi1 */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4539         .master         = &omap44xx_l4_per_hwmod,
4540         .slave          = &omap44xx_dss_dsi1_hwmod,
4541         .clk            = "l4_div_ck",
4542         .addr           = omap44xx_dss_dsi1_addrs,
4543         .user           = OCP_USER_MPU,
4544 };
4545
4546 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4547         {
4548                 .pa_start       = 0x58005000,
4549                 .pa_end         = 0x580051ff,
4550                 .flags          = ADDR_TYPE_RT
4551         },
4552         { }
4553 };
4554
4555 /* l3_main_2 -> dss_dsi2 */
4556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4557         .master         = &omap44xx_l3_main_2_hwmod,
4558         .slave          = &omap44xx_dss_dsi2_hwmod,
4559         .clk            = "dss_fck",
4560         .addr           = omap44xx_dss_dsi2_dma_addrs,
4561         .user           = OCP_USER_SDMA,
4562 };
4563
4564 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4565         {
4566                 .pa_start       = 0x48045000,
4567                 .pa_end         = 0x480451ff,
4568                 .flags          = ADDR_TYPE_RT
4569         },
4570         { }
4571 };
4572
4573 /* l4_per -> dss_dsi2 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4575         .master         = &omap44xx_l4_per_hwmod,
4576         .slave          = &omap44xx_dss_dsi2_hwmod,
4577         .clk            = "l4_div_ck",
4578         .addr           = omap44xx_dss_dsi2_addrs,
4579         .user           = OCP_USER_MPU,
4580 };
4581
4582 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4583         {
4584                 .pa_start       = 0x58006000,
4585                 .pa_end         = 0x58006fff,
4586                 .flags          = ADDR_TYPE_RT
4587         },
4588         { }
4589 };
4590
4591 /* l3_main_2 -> dss_hdmi */
4592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4593         .master         = &omap44xx_l3_main_2_hwmod,
4594         .slave          = &omap44xx_dss_hdmi_hwmod,
4595         .clk            = "dss_fck",
4596         .addr           = omap44xx_dss_hdmi_dma_addrs,
4597         .user           = OCP_USER_SDMA,
4598 };
4599
4600 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4601         {
4602                 .pa_start       = 0x48046000,
4603                 .pa_end         = 0x48046fff,
4604                 .flags          = ADDR_TYPE_RT
4605         },
4606         { }
4607 };
4608
4609 /* l4_per -> dss_hdmi */
4610 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4611         .master         = &omap44xx_l4_per_hwmod,
4612         .slave          = &omap44xx_dss_hdmi_hwmod,
4613         .clk            = "l4_div_ck",
4614         .addr           = omap44xx_dss_hdmi_addrs,
4615         .user           = OCP_USER_MPU,
4616 };
4617
4618 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4619         {
4620                 .pa_start       = 0x58002000,
4621                 .pa_end         = 0x580020ff,
4622                 .flags          = ADDR_TYPE_RT
4623         },
4624         { }
4625 };
4626
4627 /* l3_main_2 -> dss_rfbi */
4628 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4629         .master         = &omap44xx_l3_main_2_hwmod,
4630         .slave          = &omap44xx_dss_rfbi_hwmod,
4631         .clk            = "dss_fck",
4632         .addr           = omap44xx_dss_rfbi_dma_addrs,
4633         .user           = OCP_USER_SDMA,
4634 };
4635
4636 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4637         {
4638                 .pa_start       = 0x48042000,
4639                 .pa_end         = 0x480420ff,
4640                 .flags          = ADDR_TYPE_RT
4641         },
4642         { }
4643 };
4644
4645 /* l4_per -> dss_rfbi */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4647         .master         = &omap44xx_l4_per_hwmod,
4648         .slave          = &omap44xx_dss_rfbi_hwmod,
4649         .clk            = "l4_div_ck",
4650         .addr           = omap44xx_dss_rfbi_addrs,
4651         .user           = OCP_USER_MPU,
4652 };
4653
4654 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4655         {
4656                 .pa_start       = 0x58003000,
4657                 .pa_end         = 0x580030ff,
4658                 .flags          = ADDR_TYPE_RT
4659         },
4660         { }
4661 };
4662
4663 /* l3_main_2 -> dss_venc */
4664 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4665         .master         = &omap44xx_l3_main_2_hwmod,
4666         .slave          = &omap44xx_dss_venc_hwmod,
4667         .clk            = "dss_fck",
4668         .addr           = omap44xx_dss_venc_dma_addrs,
4669         .user           = OCP_USER_SDMA,
4670 };
4671
4672 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4673         {
4674                 .pa_start       = 0x48043000,
4675                 .pa_end         = 0x480430ff,
4676                 .flags          = ADDR_TYPE_RT
4677         },
4678         { }
4679 };
4680
4681 /* l4_per -> dss_venc */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4683         .master         = &omap44xx_l4_per_hwmod,
4684         .slave          = &omap44xx_dss_venc_hwmod,
4685         .clk            = "l4_div_ck",
4686         .addr           = omap44xx_dss_venc_addrs,
4687         .user           = OCP_USER_MPU,
4688 };
4689
4690 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4691         {
4692                 .pa_start       = 0x48078000,
4693                 .pa_end         = 0x48078fff,
4694                 .flags          = ADDR_TYPE_RT
4695         },
4696         { }
4697 };
4698
4699 /* l4_per -> elm */
4700 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4701         .master         = &omap44xx_l4_per_hwmod,
4702         .slave          = &omap44xx_elm_hwmod,
4703         .clk            = "l4_div_ck",
4704         .addr           = omap44xx_elm_addrs,
4705         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4706 };
4707
4708 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4709         {
4710                 .pa_start       = 0x4c000000,
4711                 .pa_end         = 0x4c0000ff,
4712                 .flags          = ADDR_TYPE_RT
4713         },
4714         { }
4715 };
4716
4717 /* emif_fw -> emif1 */
4718 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4719         .master         = &omap44xx_emif_fw_hwmod,
4720         .slave          = &omap44xx_emif1_hwmod,
4721         .clk            = "l3_div_ck",
4722         .addr           = omap44xx_emif1_addrs,
4723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4724 };
4725
4726 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4727         {
4728                 .pa_start       = 0x4d000000,
4729                 .pa_end         = 0x4d0000ff,
4730                 .flags          = ADDR_TYPE_RT
4731         },
4732         { }
4733 };
4734
4735 /* emif_fw -> emif2 */
4736 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4737         .master         = &omap44xx_emif_fw_hwmod,
4738         .slave          = &omap44xx_emif2_hwmod,
4739         .clk            = "l3_div_ck",
4740         .addr           = omap44xx_emif2_addrs,
4741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4742 };
4743
4744 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4745         {
4746                 .pa_start       = 0x4a10a000,
4747                 .pa_end         = 0x4a10a1ff,
4748                 .flags          = ADDR_TYPE_RT
4749         },
4750         { }
4751 };
4752
4753 /* l4_cfg -> fdif */
4754 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4755         .master         = &omap44xx_l4_cfg_hwmod,
4756         .slave          = &omap44xx_fdif_hwmod,
4757         .clk            = "l4_div_ck",
4758         .addr           = omap44xx_fdif_addrs,
4759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4760 };
4761
4762 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4763         {
4764                 .pa_start       = 0x4a310000,
4765                 .pa_end         = 0x4a3101ff,
4766                 .flags          = ADDR_TYPE_RT
4767         },
4768         { }
4769 };
4770
4771 /* l4_wkup -> gpio1 */
4772 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4773         .master         = &omap44xx_l4_wkup_hwmod,
4774         .slave          = &omap44xx_gpio1_hwmod,
4775         .clk            = "l4_wkup_clk_mux_ck",
4776         .addr           = omap44xx_gpio1_addrs,
4777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4778 };
4779
4780 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4781         {
4782                 .pa_start       = 0x48055000,
4783                 .pa_end         = 0x480551ff,
4784                 .flags          = ADDR_TYPE_RT
4785         },
4786         { }
4787 };
4788
4789 /* l4_per -> gpio2 */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4791         .master         = &omap44xx_l4_per_hwmod,
4792         .slave          = &omap44xx_gpio2_hwmod,
4793         .clk            = "l4_div_ck",
4794         .addr           = omap44xx_gpio2_addrs,
4795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4796 };
4797
4798 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4799         {
4800                 .pa_start       = 0x48057000,
4801                 .pa_end         = 0x480571ff,
4802                 .flags          = ADDR_TYPE_RT
4803         },
4804         { }
4805 };
4806
4807 /* l4_per -> gpio3 */
4808 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4809         .master         = &omap44xx_l4_per_hwmod,
4810         .slave          = &omap44xx_gpio3_hwmod,
4811         .clk            = "l4_div_ck",
4812         .addr           = omap44xx_gpio3_addrs,
4813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4814 };
4815
4816 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4817         {
4818                 .pa_start       = 0x48059000,
4819                 .pa_end         = 0x480591ff,
4820                 .flags          = ADDR_TYPE_RT
4821         },
4822         { }
4823 };
4824
4825 /* l4_per -> gpio4 */
4826 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4827         .master         = &omap44xx_l4_per_hwmod,
4828         .slave          = &omap44xx_gpio4_hwmod,
4829         .clk            = "l4_div_ck",
4830         .addr           = omap44xx_gpio4_addrs,
4831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4832 };
4833
4834 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4835         {
4836                 .pa_start       = 0x4805b000,
4837                 .pa_end         = 0x4805b1ff,
4838                 .flags          = ADDR_TYPE_RT
4839         },
4840         { }
4841 };
4842
4843 /* l4_per -> gpio5 */
4844 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4845         .master         = &omap44xx_l4_per_hwmod,
4846         .slave          = &omap44xx_gpio5_hwmod,
4847         .clk            = "l4_div_ck",
4848         .addr           = omap44xx_gpio5_addrs,
4849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4850 };
4851
4852 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4853         {
4854                 .pa_start       = 0x4805d000,
4855                 .pa_end         = 0x4805d1ff,
4856                 .flags          = ADDR_TYPE_RT
4857         },
4858         { }
4859 };
4860
4861 /* l4_per -> gpio6 */
4862 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4863         .master         = &omap44xx_l4_per_hwmod,
4864         .slave          = &omap44xx_gpio6_hwmod,
4865         .clk            = "l4_div_ck",
4866         .addr           = omap44xx_gpio6_addrs,
4867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4868 };
4869
4870 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4871         {
4872                 .pa_start       = 0x50000000,
4873                 .pa_end         = 0x500003ff,
4874                 .flags          = ADDR_TYPE_RT
4875         },
4876         { }
4877 };
4878
4879 /* l3_main_2 -> gpmc */
4880 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4881         .master         = &omap44xx_l3_main_2_hwmod,
4882         .slave          = &omap44xx_gpmc_hwmod,
4883         .clk            = "l3_div_ck",
4884         .addr           = omap44xx_gpmc_addrs,
4885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4886 };
4887
4888 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4889         {
4890                 .pa_start       = 0x56000000,
4891                 .pa_end         = 0x5600ffff,
4892                 .flags          = ADDR_TYPE_RT
4893         },
4894         { }
4895 };
4896
4897 /* l3_main_2 -> gpu */
4898 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4899         .master         = &omap44xx_l3_main_2_hwmod,
4900         .slave          = &omap44xx_gpu_hwmod,
4901         .clk            = "l3_div_ck",
4902         .addr           = omap44xx_gpu_addrs,
4903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4904 };
4905
4906 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4907         {
4908                 .pa_start       = 0x480b2000,
4909                 .pa_end         = 0x480b201f,
4910                 .flags          = ADDR_TYPE_RT
4911         },
4912         { }
4913 };
4914
4915 /* l4_per -> hdq1w */
4916 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4917         .master         = &omap44xx_l4_per_hwmod,
4918         .slave          = &omap44xx_hdq1w_hwmod,
4919         .clk            = "l4_div_ck",
4920         .addr           = omap44xx_hdq1w_addrs,
4921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4922 };
4923
4924 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4925         {
4926                 .pa_start       = 0x4a058000,
4927                 .pa_end         = 0x4a05bfff,
4928                 .flags          = ADDR_TYPE_RT
4929         },
4930         { }
4931 };
4932
4933 /* l4_cfg -> hsi */
4934 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4935         .master         = &omap44xx_l4_cfg_hwmod,
4936         .slave          = &omap44xx_hsi_hwmod,
4937         .clk            = "l4_div_ck",
4938         .addr           = omap44xx_hsi_addrs,
4939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4940 };
4941
4942 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4943         {
4944                 .pa_start       = 0x48070000,
4945                 .pa_end         = 0x480700ff,
4946                 .flags          = ADDR_TYPE_RT
4947         },
4948         { }
4949 };
4950
4951 /* l4_per -> i2c1 */
4952 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4953         .master         = &omap44xx_l4_per_hwmod,
4954         .slave          = &omap44xx_i2c1_hwmod,
4955         .clk            = "l4_div_ck",
4956         .addr           = omap44xx_i2c1_addrs,
4957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4958 };
4959
4960 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4961         {
4962                 .pa_start       = 0x48072000,
4963                 .pa_end         = 0x480720ff,
4964                 .flags          = ADDR_TYPE_RT
4965         },
4966         { }
4967 };
4968
4969 /* l4_per -> i2c2 */
4970 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4971         .master         = &omap44xx_l4_per_hwmod,
4972         .slave          = &omap44xx_i2c2_hwmod,
4973         .clk            = "l4_div_ck",
4974         .addr           = omap44xx_i2c2_addrs,
4975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4976 };
4977
4978 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4979         {
4980                 .pa_start       = 0x48060000,
4981                 .pa_end         = 0x480600ff,
4982                 .flags          = ADDR_TYPE_RT
4983         },
4984         { }
4985 };
4986
4987 /* l4_per -> i2c3 */
4988 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4989         .master         = &omap44xx_l4_per_hwmod,
4990         .slave          = &omap44xx_i2c3_hwmod,
4991         .clk            = "l4_div_ck",
4992         .addr           = omap44xx_i2c3_addrs,
4993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4994 };
4995
4996 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4997         {
4998                 .pa_start       = 0x48350000,
4999                 .pa_end         = 0x483500ff,
5000                 .flags          = ADDR_TYPE_RT
5001         },
5002         { }
5003 };
5004
5005 /* l4_per -> i2c4 */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5007         .master         = &omap44xx_l4_per_hwmod,
5008         .slave          = &omap44xx_i2c4_hwmod,
5009         .clk            = "l4_div_ck",
5010         .addr           = omap44xx_i2c4_addrs,
5011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5012 };
5013
5014 /* l3_main_2 -> ipu */
5015 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5016         .master         = &omap44xx_l3_main_2_hwmod,
5017         .slave          = &omap44xx_ipu_hwmod,
5018         .clk            = "l3_div_ck",
5019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5020 };
5021
5022 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5023         {
5024                 .pa_start       = 0x52000000,
5025                 .pa_end         = 0x520000ff,
5026                 .flags          = ADDR_TYPE_RT
5027         },
5028         { }
5029 };
5030
5031 /* l3_main_2 -> iss */
5032 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5033         .master         = &omap44xx_l3_main_2_hwmod,
5034         .slave          = &omap44xx_iss_hwmod,
5035         .clk            = "l3_div_ck",
5036         .addr           = omap44xx_iss_addrs,
5037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5038 };
5039
5040 /* iva -> sl2if */
5041 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5042         .master         = &omap44xx_iva_hwmod,
5043         .slave          = &omap44xx_sl2if_hwmod,
5044         .clk            = "dpll_iva_m5x2_ck",
5045         .user           = OCP_USER_IVA,
5046 };
5047
5048 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5049         {
5050                 .pa_start       = 0x5a000000,
5051                 .pa_end         = 0x5a07ffff,
5052                 .flags          = ADDR_TYPE_RT
5053         },
5054         { }
5055 };
5056
5057 /* l3_main_2 -> iva */
5058 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5059         .master         = &omap44xx_l3_main_2_hwmod,
5060         .slave          = &omap44xx_iva_hwmod,
5061         .clk            = "l3_div_ck",
5062         .addr           = omap44xx_iva_addrs,
5063         .user           = OCP_USER_MPU,
5064 };
5065
5066 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5067         {
5068                 .pa_start       = 0x4a31c000,
5069                 .pa_end         = 0x4a31c07f,
5070                 .flags          = ADDR_TYPE_RT
5071         },
5072         { }
5073 };
5074
5075 /* l4_wkup -> kbd */
5076 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5077         .master         = &omap44xx_l4_wkup_hwmod,
5078         .slave          = &omap44xx_kbd_hwmod,
5079         .clk            = "l4_wkup_clk_mux_ck",
5080         .addr           = omap44xx_kbd_addrs,
5081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5082 };
5083
5084 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5085         {
5086                 .pa_start       = 0x4a0f4000,
5087                 .pa_end         = 0x4a0f41ff,
5088                 .flags          = ADDR_TYPE_RT
5089         },
5090         { }
5091 };
5092
5093 /* l4_cfg -> mailbox */
5094 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5095         .master         = &omap44xx_l4_cfg_hwmod,
5096         .slave          = &omap44xx_mailbox_hwmod,
5097         .clk            = "l4_div_ck",
5098         .addr           = omap44xx_mailbox_addrs,
5099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5100 };
5101
5102 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5103         {
5104                 .pa_start       = 0x40128000,
5105                 .pa_end         = 0x401283ff,
5106                 .flags          = ADDR_TYPE_RT
5107         },
5108         { }
5109 };
5110
5111 /* l4_abe -> mcasp */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5113         .master         = &omap44xx_l4_abe_hwmod,
5114         .slave          = &omap44xx_mcasp_hwmod,
5115         .clk            = "ocp_abe_iclk",
5116         .addr           = omap44xx_mcasp_addrs,
5117         .user           = OCP_USER_MPU,
5118 };
5119
5120 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5121         {
5122                 .pa_start       = 0x49028000,
5123                 .pa_end         = 0x490283ff,
5124                 .flags          = ADDR_TYPE_RT
5125         },
5126         { }
5127 };
5128
5129 /* l4_abe -> mcasp (dma) */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5131         .master         = &omap44xx_l4_abe_hwmod,
5132         .slave          = &omap44xx_mcasp_hwmod,
5133         .clk            = "ocp_abe_iclk",
5134         .addr           = omap44xx_mcasp_dma_addrs,
5135         .user           = OCP_USER_SDMA,
5136 };
5137
5138 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5139         {
5140                 .name           = "mpu",
5141                 .pa_start       = 0x40122000,
5142                 .pa_end         = 0x401220ff,
5143                 .flags          = ADDR_TYPE_RT
5144         },
5145         { }
5146 };
5147
5148 /* l4_abe -> mcbsp1 */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5150         .master         = &omap44xx_l4_abe_hwmod,
5151         .slave          = &omap44xx_mcbsp1_hwmod,
5152         .clk            = "ocp_abe_iclk",
5153         .addr           = omap44xx_mcbsp1_addrs,
5154         .user           = OCP_USER_MPU,
5155 };
5156
5157 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5158         {
5159                 .name           = "dma",
5160                 .pa_start       = 0x49022000,
5161                 .pa_end         = 0x490220ff,
5162                 .flags          = ADDR_TYPE_RT
5163         },
5164         { }
5165 };
5166
5167 /* l4_abe -> mcbsp1 (dma) */
5168 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5169         .master         = &omap44xx_l4_abe_hwmod,
5170         .slave          = &omap44xx_mcbsp1_hwmod,
5171         .clk            = "ocp_abe_iclk",
5172         .addr           = omap44xx_mcbsp1_dma_addrs,
5173         .user           = OCP_USER_SDMA,
5174 };
5175
5176 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5177         {
5178                 .name           = "mpu",
5179                 .pa_start       = 0x40124000,
5180                 .pa_end         = 0x401240ff,
5181                 .flags          = ADDR_TYPE_RT
5182         },
5183         { }
5184 };
5185
5186 /* l4_abe -> mcbsp2 */
5187 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5188         .master         = &omap44xx_l4_abe_hwmod,
5189         .slave          = &omap44xx_mcbsp2_hwmod,
5190         .clk            = "ocp_abe_iclk",
5191         .addr           = omap44xx_mcbsp2_addrs,
5192         .user           = OCP_USER_MPU,
5193 };
5194
5195 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5196         {
5197                 .name           = "dma",
5198                 .pa_start       = 0x49024000,
5199                 .pa_end         = 0x490240ff,
5200                 .flags          = ADDR_TYPE_RT
5201         },
5202         { }
5203 };
5204
5205 /* l4_abe -> mcbsp2 (dma) */
5206 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5207         .master         = &omap44xx_l4_abe_hwmod,
5208         .slave          = &omap44xx_mcbsp2_hwmod,
5209         .clk            = "ocp_abe_iclk",
5210         .addr           = omap44xx_mcbsp2_dma_addrs,
5211         .user           = OCP_USER_SDMA,
5212 };
5213
5214 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5215         {
5216                 .name           = "mpu",
5217                 .pa_start       = 0x40126000,
5218                 .pa_end         = 0x401260ff,
5219                 .flags          = ADDR_TYPE_RT
5220         },
5221         { }
5222 };
5223
5224 /* l4_abe -> mcbsp3 */
5225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5226         .master         = &omap44xx_l4_abe_hwmod,
5227         .slave          = &omap44xx_mcbsp3_hwmod,
5228         .clk            = "ocp_abe_iclk",
5229         .addr           = omap44xx_mcbsp3_addrs,
5230         .user           = OCP_USER_MPU,
5231 };
5232
5233 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5234         {
5235                 .name           = "dma",
5236                 .pa_start       = 0x49026000,
5237                 .pa_end         = 0x490260ff,
5238                 .flags          = ADDR_TYPE_RT
5239         },
5240         { }
5241 };
5242
5243 /* l4_abe -> mcbsp3 (dma) */
5244 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5245         .master         = &omap44xx_l4_abe_hwmod,
5246         .slave          = &omap44xx_mcbsp3_hwmod,
5247         .clk            = "ocp_abe_iclk",
5248         .addr           = omap44xx_mcbsp3_dma_addrs,
5249         .user           = OCP_USER_SDMA,
5250 };
5251
5252 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5253         {
5254                 .pa_start       = 0x48096000,
5255                 .pa_end         = 0x480960ff,
5256                 .flags          = ADDR_TYPE_RT
5257         },
5258         { }
5259 };
5260
5261 /* l4_per -> mcbsp4 */
5262 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5263         .master         = &omap44xx_l4_per_hwmod,
5264         .slave          = &omap44xx_mcbsp4_hwmod,
5265         .clk            = "l4_div_ck",
5266         .addr           = omap44xx_mcbsp4_addrs,
5267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5268 };
5269
5270 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5271         {
5272                 .name           = "mpu",
5273                 .pa_start       = 0x40132000,
5274                 .pa_end         = 0x4013207f,
5275                 .flags          = ADDR_TYPE_RT
5276         },
5277         { }
5278 };
5279
5280 /* l4_abe -> mcpdm */
5281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5282         .master         = &omap44xx_l4_abe_hwmod,
5283         .slave          = &omap44xx_mcpdm_hwmod,
5284         .clk            = "ocp_abe_iclk",
5285         .addr           = omap44xx_mcpdm_addrs,
5286         .user           = OCP_USER_MPU,
5287 };
5288
5289 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5290         {
5291                 .name           = "dma",
5292                 .pa_start       = 0x49032000,
5293                 .pa_end         = 0x4903207f,
5294                 .flags          = ADDR_TYPE_RT
5295         },
5296         { }
5297 };
5298
5299 /* l4_abe -> mcpdm (dma) */
5300 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5301         .master         = &omap44xx_l4_abe_hwmod,
5302         .slave          = &omap44xx_mcpdm_hwmod,
5303         .clk            = "ocp_abe_iclk",
5304         .addr           = omap44xx_mcpdm_dma_addrs,
5305         .user           = OCP_USER_SDMA,
5306 };
5307
5308 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5309         {
5310                 .pa_start       = 0x48098000,
5311                 .pa_end         = 0x480981ff,
5312                 .flags          = ADDR_TYPE_RT
5313         },
5314         { }
5315 };
5316
5317 /* l4_per -> mcspi1 */
5318 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5319         .master         = &omap44xx_l4_per_hwmod,
5320         .slave          = &omap44xx_mcspi1_hwmod,
5321         .clk            = "l4_div_ck",
5322         .addr           = omap44xx_mcspi1_addrs,
5323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5324 };
5325
5326 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5327         {
5328                 .pa_start       = 0x4809a000,
5329                 .pa_end         = 0x4809a1ff,
5330                 .flags          = ADDR_TYPE_RT
5331         },
5332         { }
5333 };
5334
5335 /* l4_per -> mcspi2 */
5336 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5337         .master         = &omap44xx_l4_per_hwmod,
5338         .slave          = &omap44xx_mcspi2_hwmod,
5339         .clk            = "l4_div_ck",
5340         .addr           = omap44xx_mcspi2_addrs,
5341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5342 };
5343
5344 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5345         {
5346                 .pa_start       = 0x480b8000,
5347                 .pa_end         = 0x480b81ff,
5348                 .flags          = ADDR_TYPE_RT
5349         },
5350         { }
5351 };
5352
5353 /* l4_per -> mcspi3 */
5354 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5355         .master         = &omap44xx_l4_per_hwmod,
5356         .slave          = &omap44xx_mcspi3_hwmod,
5357         .clk            = "l4_div_ck",
5358         .addr           = omap44xx_mcspi3_addrs,
5359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5360 };
5361
5362 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5363         {
5364                 .pa_start       = 0x480ba000,
5365                 .pa_end         = 0x480ba1ff,
5366                 .flags          = ADDR_TYPE_RT
5367         },
5368         { }
5369 };
5370
5371 /* l4_per -> mcspi4 */
5372 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5373         .master         = &omap44xx_l4_per_hwmod,
5374         .slave          = &omap44xx_mcspi4_hwmod,
5375         .clk            = "l4_div_ck",
5376         .addr           = omap44xx_mcspi4_addrs,
5377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5378 };
5379
5380 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5381         {
5382                 .pa_start       = 0x4809c000,
5383                 .pa_end         = 0x4809c3ff,
5384                 .flags          = ADDR_TYPE_RT
5385         },
5386         { }
5387 };
5388
5389 /* l4_per -> mmc1 */
5390 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5391         .master         = &omap44xx_l4_per_hwmod,
5392         .slave          = &omap44xx_mmc1_hwmod,
5393         .clk            = "l4_div_ck",
5394         .addr           = omap44xx_mmc1_addrs,
5395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5396 };
5397
5398 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5399         {
5400                 .pa_start       = 0x480b4000,
5401                 .pa_end         = 0x480b43ff,
5402                 .flags          = ADDR_TYPE_RT
5403         },
5404         { }
5405 };
5406
5407 /* l4_per -> mmc2 */
5408 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5409         .master         = &omap44xx_l4_per_hwmod,
5410         .slave          = &omap44xx_mmc2_hwmod,
5411         .clk            = "l4_div_ck",
5412         .addr           = omap44xx_mmc2_addrs,
5413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5414 };
5415
5416 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5417         {
5418                 .pa_start       = 0x480ad000,
5419                 .pa_end         = 0x480ad3ff,
5420                 .flags          = ADDR_TYPE_RT
5421         },
5422         { }
5423 };
5424
5425 /* l4_per -> mmc3 */
5426 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5427         .master         = &omap44xx_l4_per_hwmod,
5428         .slave          = &omap44xx_mmc3_hwmod,
5429         .clk            = "l4_div_ck",
5430         .addr           = omap44xx_mmc3_addrs,
5431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5432 };
5433
5434 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5435         {
5436                 .pa_start       = 0x480d1000,
5437                 .pa_end         = 0x480d13ff,
5438                 .flags          = ADDR_TYPE_RT
5439         },
5440         { }
5441 };
5442
5443 /* l4_per -> mmc4 */
5444 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5445         .master         = &omap44xx_l4_per_hwmod,
5446         .slave          = &omap44xx_mmc4_hwmod,
5447         .clk            = "l4_div_ck",
5448         .addr           = omap44xx_mmc4_addrs,
5449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5450 };
5451
5452 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5453         {
5454                 .pa_start       = 0x480d5000,
5455                 .pa_end         = 0x480d53ff,
5456                 .flags          = ADDR_TYPE_RT
5457         },
5458         { }
5459 };
5460
5461 /* l4_per -> mmc5 */
5462 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5463         .master         = &omap44xx_l4_per_hwmod,
5464         .slave          = &omap44xx_mmc5_hwmod,
5465         .clk            = "l4_div_ck",
5466         .addr           = omap44xx_mmc5_addrs,
5467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5468 };
5469
5470 /* l3_main_2 -> ocmc_ram */
5471 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5472         .master         = &omap44xx_l3_main_2_hwmod,
5473         .slave          = &omap44xx_ocmc_ram_hwmod,
5474         .clk            = "l3_div_ck",
5475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5476 };
5477
5478 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5479         {
5480                 .pa_start       = 0x4a0ad000,
5481                 .pa_end         = 0x4a0ad01f,
5482                 .flags          = ADDR_TYPE_RT
5483         },
5484         { }
5485 };
5486
5487 /* l4_cfg -> ocp2scp_usb_phy */
5488 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5489         .master         = &omap44xx_l4_cfg_hwmod,
5490         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5491         .clk            = "l4_div_ck",
5492         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5494 };
5495
5496 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5497         {
5498                 .pa_start       = 0x48243000,
5499                 .pa_end         = 0x48243fff,
5500                 .flags          = ADDR_TYPE_RT
5501         },
5502         { }
5503 };
5504
5505 /* mpu_private -> prcm_mpu */
5506 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5507         .master         = &omap44xx_mpu_private_hwmod,
5508         .slave          = &omap44xx_prcm_mpu_hwmod,
5509         .clk            = "l3_div_ck",
5510         .addr           = omap44xx_prcm_mpu_addrs,
5511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5512 };
5513
5514 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5515         {
5516                 .pa_start       = 0x4a004000,
5517                 .pa_end         = 0x4a004fff,
5518                 .flags          = ADDR_TYPE_RT
5519         },
5520         { }
5521 };
5522
5523 /* l4_wkup -> cm_core_aon */
5524 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5525         .master         = &omap44xx_l4_wkup_hwmod,
5526         .slave          = &omap44xx_cm_core_aon_hwmod,
5527         .clk            = "l4_wkup_clk_mux_ck",
5528         .addr           = omap44xx_cm_core_aon_addrs,
5529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5530 };
5531
5532 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5533         {
5534                 .pa_start       = 0x4a008000,
5535                 .pa_end         = 0x4a009fff,
5536                 .flags          = ADDR_TYPE_RT
5537         },
5538         { }
5539 };
5540
5541 /* l4_cfg -> cm_core */
5542 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5543         .master         = &omap44xx_l4_cfg_hwmod,
5544         .slave          = &omap44xx_cm_core_hwmod,
5545         .clk            = "l4_div_ck",
5546         .addr           = omap44xx_cm_core_addrs,
5547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5548 };
5549
5550 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5551         {
5552                 .pa_start       = 0x4a306000,
5553                 .pa_end         = 0x4a307fff,
5554                 .flags          = ADDR_TYPE_RT
5555         },
5556         { }
5557 };
5558
5559 /* l4_wkup -> prm */
5560 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5561         .master         = &omap44xx_l4_wkup_hwmod,
5562         .slave          = &omap44xx_prm_hwmod,
5563         .clk            = "l4_wkup_clk_mux_ck",
5564         .addr           = omap44xx_prm_addrs,
5565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5566 };
5567
5568 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5569         {
5570                 .pa_start       = 0x4a30a000,
5571                 .pa_end         = 0x4a30a7ff,
5572                 .flags          = ADDR_TYPE_RT
5573         },
5574         { }
5575 };
5576
5577 /* l4_wkup -> scrm */
5578 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5579         .master         = &omap44xx_l4_wkup_hwmod,
5580         .slave          = &omap44xx_scrm_hwmod,
5581         .clk            = "l4_wkup_clk_mux_ck",
5582         .addr           = omap44xx_scrm_addrs,
5583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5584 };
5585
5586 /* l3_main_2 -> sl2if */
5587 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5588         .master         = &omap44xx_l3_main_2_hwmod,
5589         .slave          = &omap44xx_sl2if_hwmod,
5590         .clk            = "l3_div_ck",
5591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5592 };
5593
5594 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5595         {
5596                 .pa_start       = 0x4012c000,
5597                 .pa_end         = 0x4012c3ff,
5598                 .flags          = ADDR_TYPE_RT
5599         },
5600         { }
5601 };
5602
5603 /* l4_abe -> slimbus1 */
5604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5605         .master         = &omap44xx_l4_abe_hwmod,
5606         .slave          = &omap44xx_slimbus1_hwmod,
5607         .clk            = "ocp_abe_iclk",
5608         .addr           = omap44xx_slimbus1_addrs,
5609         .user           = OCP_USER_MPU,
5610 };
5611
5612 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5613         {
5614                 .pa_start       = 0x4902c000,
5615                 .pa_end         = 0x4902c3ff,
5616                 .flags          = ADDR_TYPE_RT
5617         },
5618         { }
5619 };
5620
5621 /* l4_abe -> slimbus1 (dma) */
5622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5623         .master         = &omap44xx_l4_abe_hwmod,
5624         .slave          = &omap44xx_slimbus1_hwmod,
5625         .clk            = "ocp_abe_iclk",
5626         .addr           = omap44xx_slimbus1_dma_addrs,
5627         .user           = OCP_USER_SDMA,
5628 };
5629
5630 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5631         {
5632                 .pa_start       = 0x48076000,
5633                 .pa_end         = 0x480763ff,
5634                 .flags          = ADDR_TYPE_RT
5635         },
5636         { }
5637 };
5638
5639 /* l4_per -> slimbus2 */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5641         .master         = &omap44xx_l4_per_hwmod,
5642         .slave          = &omap44xx_slimbus2_hwmod,
5643         .clk            = "l4_div_ck",
5644         .addr           = omap44xx_slimbus2_addrs,
5645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5646 };
5647
5648 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5649         {
5650                 .pa_start       = 0x4a0dd000,
5651                 .pa_end         = 0x4a0dd03f,
5652                 .flags          = ADDR_TYPE_RT
5653         },
5654         { }
5655 };
5656
5657 /* l4_cfg -> smartreflex_core */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5659         .master         = &omap44xx_l4_cfg_hwmod,
5660         .slave          = &omap44xx_smartreflex_core_hwmod,
5661         .clk            = "l4_div_ck",
5662         .addr           = omap44xx_smartreflex_core_addrs,
5663         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5664 };
5665
5666 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5667         {
5668                 .pa_start       = 0x4a0db000,
5669                 .pa_end         = 0x4a0db03f,
5670                 .flags          = ADDR_TYPE_RT
5671         },
5672         { }
5673 };
5674
5675 /* l4_cfg -> smartreflex_iva */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5677         .master         = &omap44xx_l4_cfg_hwmod,
5678         .slave          = &omap44xx_smartreflex_iva_hwmod,
5679         .clk            = "l4_div_ck",
5680         .addr           = omap44xx_smartreflex_iva_addrs,
5681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5682 };
5683
5684 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5685         {
5686                 .pa_start       = 0x4a0d9000,
5687                 .pa_end         = 0x4a0d903f,
5688                 .flags          = ADDR_TYPE_RT
5689         },
5690         { }
5691 };
5692
5693 /* l4_cfg -> smartreflex_mpu */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5695         .master         = &omap44xx_l4_cfg_hwmod,
5696         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5697         .clk            = "l4_div_ck",
5698         .addr           = omap44xx_smartreflex_mpu_addrs,
5699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5700 };
5701
5702 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5703         {
5704                 .pa_start       = 0x4a0f6000,
5705                 .pa_end         = 0x4a0f6fff,
5706                 .flags          = ADDR_TYPE_RT
5707         },
5708         { }
5709 };
5710
5711 /* l4_cfg -> spinlock */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5713         .master         = &omap44xx_l4_cfg_hwmod,
5714         .slave          = &omap44xx_spinlock_hwmod,
5715         .clk            = "l4_div_ck",
5716         .addr           = omap44xx_spinlock_addrs,
5717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5718 };
5719
5720 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5721         {
5722                 .pa_start       = 0x4a318000,
5723                 .pa_end         = 0x4a31807f,
5724                 .flags          = ADDR_TYPE_RT
5725         },
5726         { }
5727 };
5728
5729 /* l4_wkup -> timer1 */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5731         .master         = &omap44xx_l4_wkup_hwmod,
5732         .slave          = &omap44xx_timer1_hwmod,
5733         .clk            = "l4_wkup_clk_mux_ck",
5734         .addr           = omap44xx_timer1_addrs,
5735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5736 };
5737
5738 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5739         {
5740                 .pa_start       = 0x48032000,
5741                 .pa_end         = 0x4803207f,
5742                 .flags          = ADDR_TYPE_RT
5743         },
5744         { }
5745 };
5746
5747 /* l4_per -> timer2 */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5749         .master         = &omap44xx_l4_per_hwmod,
5750         .slave          = &omap44xx_timer2_hwmod,
5751         .clk            = "l4_div_ck",
5752         .addr           = omap44xx_timer2_addrs,
5753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5754 };
5755
5756 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5757         {
5758                 .pa_start       = 0x48034000,
5759                 .pa_end         = 0x4803407f,
5760                 .flags          = ADDR_TYPE_RT
5761         },
5762         { }
5763 };
5764
5765 /* l4_per -> timer3 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5767         .master         = &omap44xx_l4_per_hwmod,
5768         .slave          = &omap44xx_timer3_hwmod,
5769         .clk            = "l4_div_ck",
5770         .addr           = omap44xx_timer3_addrs,
5771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5772 };
5773
5774 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5775         {
5776                 .pa_start       = 0x48036000,
5777                 .pa_end         = 0x4803607f,
5778                 .flags          = ADDR_TYPE_RT
5779         },
5780         { }
5781 };
5782
5783 /* l4_per -> timer4 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5785         .master         = &omap44xx_l4_per_hwmod,
5786         .slave          = &omap44xx_timer4_hwmod,
5787         .clk            = "l4_div_ck",
5788         .addr           = omap44xx_timer4_addrs,
5789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5790 };
5791
5792 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5793         {
5794                 .pa_start       = 0x40138000,
5795                 .pa_end         = 0x4013807f,
5796                 .flags          = ADDR_TYPE_RT
5797         },
5798         { }
5799 };
5800
5801 /* l4_abe -> timer5 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5803         .master         = &omap44xx_l4_abe_hwmod,
5804         .slave          = &omap44xx_timer5_hwmod,
5805         .clk            = "ocp_abe_iclk",
5806         .addr           = omap44xx_timer5_addrs,
5807         .user           = OCP_USER_MPU,
5808 };
5809
5810 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5811         {
5812                 .pa_start       = 0x49038000,
5813                 .pa_end         = 0x4903807f,
5814                 .flags          = ADDR_TYPE_RT
5815         },
5816         { }
5817 };
5818
5819 /* l4_abe -> timer5 (dma) */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5821         .master         = &omap44xx_l4_abe_hwmod,
5822         .slave          = &omap44xx_timer5_hwmod,
5823         .clk            = "ocp_abe_iclk",
5824         .addr           = omap44xx_timer5_dma_addrs,
5825         .user           = OCP_USER_SDMA,
5826 };
5827
5828 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5829         {
5830                 .pa_start       = 0x4013a000,
5831                 .pa_end         = 0x4013a07f,
5832                 .flags          = ADDR_TYPE_RT
5833         },
5834         { }
5835 };
5836
5837 /* l4_abe -> timer6 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5839         .master         = &omap44xx_l4_abe_hwmod,
5840         .slave          = &omap44xx_timer6_hwmod,
5841         .clk            = "ocp_abe_iclk",
5842         .addr           = omap44xx_timer6_addrs,
5843         .user           = OCP_USER_MPU,
5844 };
5845
5846 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5847         {
5848                 .pa_start       = 0x4903a000,
5849                 .pa_end         = 0x4903a07f,
5850                 .flags          = ADDR_TYPE_RT
5851         },
5852         { }
5853 };
5854
5855 /* l4_abe -> timer6 (dma) */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5857         .master         = &omap44xx_l4_abe_hwmod,
5858         .slave          = &omap44xx_timer6_hwmod,
5859         .clk            = "ocp_abe_iclk",
5860         .addr           = omap44xx_timer6_dma_addrs,
5861         .user           = OCP_USER_SDMA,
5862 };
5863
5864 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5865         {
5866                 .pa_start       = 0x4013c000,
5867                 .pa_end         = 0x4013c07f,
5868                 .flags          = ADDR_TYPE_RT
5869         },
5870         { }
5871 };
5872
5873 /* l4_abe -> timer7 */
5874 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5875         .master         = &omap44xx_l4_abe_hwmod,
5876         .slave          = &omap44xx_timer7_hwmod,
5877         .clk            = "ocp_abe_iclk",
5878         .addr           = omap44xx_timer7_addrs,
5879         .user           = OCP_USER_MPU,
5880 };
5881
5882 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5883         {
5884                 .pa_start       = 0x4903c000,
5885                 .pa_end         = 0x4903c07f,
5886                 .flags          = ADDR_TYPE_RT
5887         },
5888         { }
5889 };
5890
5891 /* l4_abe -> timer7 (dma) */
5892 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5893         .master         = &omap44xx_l4_abe_hwmod,
5894         .slave          = &omap44xx_timer7_hwmod,
5895         .clk            = "ocp_abe_iclk",
5896         .addr           = omap44xx_timer7_dma_addrs,
5897         .user           = OCP_USER_SDMA,
5898 };
5899
5900 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5901         {
5902                 .pa_start       = 0x4013e000,
5903                 .pa_end         = 0x4013e07f,
5904                 .flags          = ADDR_TYPE_RT
5905         },
5906         { }
5907 };
5908
5909 /* l4_abe -> timer8 */
5910 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5911         .master         = &omap44xx_l4_abe_hwmod,
5912         .slave          = &omap44xx_timer8_hwmod,
5913         .clk            = "ocp_abe_iclk",
5914         .addr           = omap44xx_timer8_addrs,
5915         .user           = OCP_USER_MPU,
5916 };
5917
5918 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5919         {
5920                 .pa_start       = 0x4903e000,
5921                 .pa_end         = 0x4903e07f,
5922                 .flags          = ADDR_TYPE_RT
5923         },
5924         { }
5925 };
5926
5927 /* l4_abe -> timer8 (dma) */
5928 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5929         .master         = &omap44xx_l4_abe_hwmod,
5930         .slave          = &omap44xx_timer8_hwmod,
5931         .clk            = "ocp_abe_iclk",
5932         .addr           = omap44xx_timer8_dma_addrs,
5933         .user           = OCP_USER_SDMA,
5934 };
5935
5936 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5937         {
5938                 .pa_start       = 0x4803e000,
5939                 .pa_end         = 0x4803e07f,
5940                 .flags          = ADDR_TYPE_RT
5941         },
5942         { }
5943 };
5944
5945 /* l4_per -> timer9 */
5946 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5947         .master         = &omap44xx_l4_per_hwmod,
5948         .slave          = &omap44xx_timer9_hwmod,
5949         .clk            = "l4_div_ck",
5950         .addr           = omap44xx_timer9_addrs,
5951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5952 };
5953
5954 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5955         {
5956                 .pa_start       = 0x48086000,
5957                 .pa_end         = 0x4808607f,
5958                 .flags          = ADDR_TYPE_RT
5959         },
5960         { }
5961 };
5962
5963 /* l4_per -> timer10 */
5964 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5965         .master         = &omap44xx_l4_per_hwmod,
5966         .slave          = &omap44xx_timer10_hwmod,
5967         .clk            = "l4_div_ck",
5968         .addr           = omap44xx_timer10_addrs,
5969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5970 };
5971
5972 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5973         {
5974                 .pa_start       = 0x48088000,
5975                 .pa_end         = 0x4808807f,
5976                 .flags          = ADDR_TYPE_RT
5977         },
5978         { }
5979 };
5980
5981 /* l4_per -> timer11 */
5982 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5983         .master         = &omap44xx_l4_per_hwmod,
5984         .slave          = &omap44xx_timer11_hwmod,
5985         .clk            = "l4_div_ck",
5986         .addr           = omap44xx_timer11_addrs,
5987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5988 };
5989
5990 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5991         {
5992                 .pa_start       = 0x4806a000,
5993                 .pa_end         = 0x4806a0ff,
5994                 .flags          = ADDR_TYPE_RT
5995         },
5996         { }
5997 };
5998
5999 /* l4_per -> uart1 */
6000 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6001         .master         = &omap44xx_l4_per_hwmod,
6002         .slave          = &omap44xx_uart1_hwmod,
6003         .clk            = "l4_div_ck",
6004         .addr           = omap44xx_uart1_addrs,
6005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6006 };
6007
6008 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6009         {
6010                 .pa_start       = 0x4806c000,
6011                 .pa_end         = 0x4806c0ff,
6012                 .flags          = ADDR_TYPE_RT
6013         },
6014         { }
6015 };
6016
6017 /* l4_per -> uart2 */
6018 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6019         .master         = &omap44xx_l4_per_hwmod,
6020         .slave          = &omap44xx_uart2_hwmod,
6021         .clk            = "l4_div_ck",
6022         .addr           = omap44xx_uart2_addrs,
6023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6024 };
6025
6026 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6027         {
6028                 .pa_start       = 0x48020000,
6029                 .pa_end         = 0x480200ff,
6030                 .flags          = ADDR_TYPE_RT
6031         },
6032         { }
6033 };
6034
6035 /* l4_per -> uart3 */
6036 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6037         .master         = &omap44xx_l4_per_hwmod,
6038         .slave          = &omap44xx_uart3_hwmod,
6039         .clk            = "l4_div_ck",
6040         .addr           = omap44xx_uart3_addrs,
6041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6042 };
6043
6044 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6045         {
6046                 .pa_start       = 0x4806e000,
6047                 .pa_end         = 0x4806e0ff,
6048                 .flags          = ADDR_TYPE_RT
6049         },
6050         { }
6051 };
6052
6053 /* l4_per -> uart4 */
6054 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6055         .master         = &omap44xx_l4_per_hwmod,
6056         .slave          = &omap44xx_uart4_hwmod,
6057         .clk            = "l4_div_ck",
6058         .addr           = omap44xx_uart4_addrs,
6059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6060 };
6061
6062 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6063         {
6064                 .pa_start       = 0x4a0a9000,
6065                 .pa_end         = 0x4a0a93ff,
6066                 .flags          = ADDR_TYPE_RT
6067         },
6068         { }
6069 };
6070
6071 /* l4_cfg -> usb_host_fs */
6072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6073         .master         = &omap44xx_l4_cfg_hwmod,
6074         .slave          = &omap44xx_usb_host_fs_hwmod,
6075         .clk            = "l4_div_ck",
6076         .addr           = omap44xx_usb_host_fs_addrs,
6077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6078 };
6079
6080 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6081         {
6082                 .name           = "uhh",
6083                 .pa_start       = 0x4a064000,
6084                 .pa_end         = 0x4a0647ff,
6085                 .flags          = ADDR_TYPE_RT
6086         },
6087         {
6088                 .name           = "ohci",
6089                 .pa_start       = 0x4a064800,
6090                 .pa_end         = 0x4a064bff,
6091         },
6092         {
6093                 .name           = "ehci",
6094                 .pa_start       = 0x4a064c00,
6095                 .pa_end         = 0x4a064fff,
6096         },
6097         {}
6098 };
6099
6100 /* l4_cfg -> usb_host_hs */
6101 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6102         .master         = &omap44xx_l4_cfg_hwmod,
6103         .slave          = &omap44xx_usb_host_hs_hwmod,
6104         .clk            = "l4_div_ck",
6105         .addr           = omap44xx_usb_host_hs_addrs,
6106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6107 };
6108
6109 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6110         {
6111                 .pa_start       = 0x4a0ab000,
6112                 .pa_end         = 0x4a0ab7ff,
6113                 .flags          = ADDR_TYPE_RT
6114         },
6115         {
6116                 /* XXX: Remove this once control module driver is in place */
6117                 .pa_start       = 0x4a00233c,
6118                 .pa_end         = 0x4a00233f,
6119                 .flags          = ADDR_TYPE_RT
6120         },
6121         { }
6122 };
6123
6124 /* l4_cfg -> usb_otg_hs */
6125 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6126         .master         = &omap44xx_l4_cfg_hwmod,
6127         .slave          = &omap44xx_usb_otg_hs_hwmod,
6128         .clk            = "l4_div_ck",
6129         .addr           = omap44xx_usb_otg_hs_addrs,
6130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6131 };
6132
6133 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6134         {
6135                 .name           = "tll",
6136                 .pa_start       = 0x4a062000,
6137                 .pa_end         = 0x4a063fff,
6138                 .flags          = ADDR_TYPE_RT
6139         },
6140         {}
6141 };
6142
6143 /* l4_cfg -> usb_tll_hs */
6144 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6145         .master         = &omap44xx_l4_cfg_hwmod,
6146         .slave          = &omap44xx_usb_tll_hs_hwmod,
6147         .clk            = "l4_div_ck",
6148         .addr           = omap44xx_usb_tll_hs_addrs,
6149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6150 };
6151
6152 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6153         {
6154                 .pa_start       = 0x4a314000,
6155                 .pa_end         = 0x4a31407f,
6156                 .flags          = ADDR_TYPE_RT
6157         },
6158         { }
6159 };
6160
6161 /* l4_wkup -> wd_timer2 */
6162 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6163         .master         = &omap44xx_l4_wkup_hwmod,
6164         .slave          = &omap44xx_wd_timer2_hwmod,
6165         .clk            = "l4_wkup_clk_mux_ck",
6166         .addr           = omap44xx_wd_timer2_addrs,
6167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6168 };
6169
6170 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6171         {
6172                 .pa_start       = 0x40130000,
6173                 .pa_end         = 0x4013007f,
6174                 .flags          = ADDR_TYPE_RT
6175         },
6176         { }
6177 };
6178
6179 /* l4_abe -> wd_timer3 */
6180 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6181         .master         = &omap44xx_l4_abe_hwmod,
6182         .slave          = &omap44xx_wd_timer3_hwmod,
6183         .clk            = "ocp_abe_iclk",
6184         .addr           = omap44xx_wd_timer3_addrs,
6185         .user           = OCP_USER_MPU,
6186 };
6187
6188 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6189         {
6190                 .pa_start       = 0x49030000,
6191                 .pa_end         = 0x4903007f,
6192                 .flags          = ADDR_TYPE_RT
6193         },
6194         { }
6195 };
6196
6197 /* l4_abe -> wd_timer3 (dma) */
6198 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6199         .master         = &omap44xx_l4_abe_hwmod,
6200         .slave          = &omap44xx_wd_timer3_hwmod,
6201         .clk            = "ocp_abe_iclk",
6202         .addr           = omap44xx_wd_timer3_dma_addrs,
6203         .user           = OCP_USER_SDMA,
6204 };
6205
6206 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6207         &omap44xx_c2c__c2c_target_fw,
6208         &omap44xx_l4_cfg__c2c_target_fw,
6209         &omap44xx_l3_main_1__dmm,
6210         &omap44xx_mpu__dmm,
6211         &omap44xx_c2c__emif_fw,
6212         &omap44xx_dmm__emif_fw,
6213         &omap44xx_l4_cfg__emif_fw,
6214         &omap44xx_iva__l3_instr,
6215         &omap44xx_l3_main_3__l3_instr,
6216         &omap44xx_ocp_wp_noc__l3_instr,
6217         &omap44xx_dsp__l3_main_1,
6218         &omap44xx_dss__l3_main_1,
6219         &omap44xx_l3_main_2__l3_main_1,
6220         &omap44xx_l4_cfg__l3_main_1,
6221         &omap44xx_mmc1__l3_main_1,
6222         &omap44xx_mmc2__l3_main_1,
6223         &omap44xx_mpu__l3_main_1,
6224         &omap44xx_c2c_target_fw__l3_main_2,
6225         &omap44xx_debugss__l3_main_2,
6226         &omap44xx_dma_system__l3_main_2,
6227         &omap44xx_fdif__l3_main_2,
6228         &omap44xx_gpu__l3_main_2,
6229         &omap44xx_hsi__l3_main_2,
6230         &omap44xx_ipu__l3_main_2,
6231         &omap44xx_iss__l3_main_2,
6232         &omap44xx_iva__l3_main_2,
6233         &omap44xx_l3_main_1__l3_main_2,
6234         &omap44xx_l4_cfg__l3_main_2,
6235         /* &omap44xx_usb_host_fs__l3_main_2, */
6236         &omap44xx_usb_host_hs__l3_main_2,
6237         &omap44xx_usb_otg_hs__l3_main_2,
6238         &omap44xx_l3_main_1__l3_main_3,
6239         &omap44xx_l3_main_2__l3_main_3,
6240         &omap44xx_l4_cfg__l3_main_3,
6241         /* &omap44xx_aess__l4_abe, */
6242         &omap44xx_dsp__l4_abe,
6243         &omap44xx_l3_main_1__l4_abe,
6244         &omap44xx_mpu__l4_abe,
6245         &omap44xx_l3_main_1__l4_cfg,
6246         &omap44xx_l3_main_2__l4_per,
6247         &omap44xx_l4_cfg__l4_wkup,
6248         &omap44xx_mpu__mpu_private,
6249         &omap44xx_l4_cfg__ocp_wp_noc,
6250         /* &omap44xx_l4_abe__aess, */
6251         /* &omap44xx_l4_abe__aess_dma, */
6252         &omap44xx_l3_main_2__c2c,
6253         &omap44xx_l4_wkup__counter_32k,
6254         &omap44xx_l4_cfg__ctrl_module_core,
6255         &omap44xx_l4_cfg__ctrl_module_pad_core,
6256         &omap44xx_l4_wkup__ctrl_module_wkup,
6257         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6258         &omap44xx_l3_instr__debugss,
6259         &omap44xx_l4_cfg__dma_system,
6260         &omap44xx_l4_abe__dmic,
6261         &omap44xx_l4_abe__dmic_dma,
6262         &omap44xx_dsp__iva,
6263         /* &omap44xx_dsp__sl2if, */
6264         &omap44xx_l4_cfg__dsp,
6265         &omap44xx_l3_main_2__dss,
6266         &omap44xx_l4_per__dss,
6267         &omap44xx_l3_main_2__dss_dispc,
6268         &omap44xx_l4_per__dss_dispc,
6269         &omap44xx_l3_main_2__dss_dsi1,
6270         &omap44xx_l4_per__dss_dsi1,
6271         &omap44xx_l3_main_2__dss_dsi2,
6272         &omap44xx_l4_per__dss_dsi2,
6273         &omap44xx_l3_main_2__dss_hdmi,
6274         &omap44xx_l4_per__dss_hdmi,
6275         &omap44xx_l3_main_2__dss_rfbi,
6276         &omap44xx_l4_per__dss_rfbi,
6277         &omap44xx_l3_main_2__dss_venc,
6278         &omap44xx_l4_per__dss_venc,
6279         &omap44xx_l4_per__elm,
6280         &omap44xx_emif_fw__emif1,
6281         &omap44xx_emif_fw__emif2,
6282         &omap44xx_l4_cfg__fdif,
6283         &omap44xx_l4_wkup__gpio1,
6284         &omap44xx_l4_per__gpio2,
6285         &omap44xx_l4_per__gpio3,
6286         &omap44xx_l4_per__gpio4,
6287         &omap44xx_l4_per__gpio5,
6288         &omap44xx_l4_per__gpio6,
6289         &omap44xx_l3_main_2__gpmc,
6290         &omap44xx_l3_main_2__gpu,
6291         &omap44xx_l4_per__hdq1w,
6292         &omap44xx_l4_cfg__hsi,
6293         &omap44xx_l4_per__i2c1,
6294         &omap44xx_l4_per__i2c2,
6295         &omap44xx_l4_per__i2c3,
6296         &omap44xx_l4_per__i2c4,
6297         &omap44xx_l3_main_2__ipu,
6298         &omap44xx_l3_main_2__iss,
6299         /* &omap44xx_iva__sl2if, */
6300         &omap44xx_l3_main_2__iva,
6301         &omap44xx_l4_wkup__kbd,
6302         &omap44xx_l4_cfg__mailbox,
6303         &omap44xx_l4_abe__mcasp,
6304         &omap44xx_l4_abe__mcasp_dma,
6305         &omap44xx_l4_abe__mcbsp1,
6306         &omap44xx_l4_abe__mcbsp1_dma,
6307         &omap44xx_l4_abe__mcbsp2,
6308         &omap44xx_l4_abe__mcbsp2_dma,
6309         &omap44xx_l4_abe__mcbsp3,
6310         &omap44xx_l4_abe__mcbsp3_dma,
6311         &omap44xx_l4_per__mcbsp4,
6312         &omap44xx_l4_abe__mcpdm,
6313         &omap44xx_l4_abe__mcpdm_dma,
6314         &omap44xx_l4_per__mcspi1,
6315         &omap44xx_l4_per__mcspi2,
6316         &omap44xx_l4_per__mcspi3,
6317         &omap44xx_l4_per__mcspi4,
6318         &omap44xx_l4_per__mmc1,
6319         &omap44xx_l4_per__mmc2,
6320         &omap44xx_l4_per__mmc3,
6321         &omap44xx_l4_per__mmc4,
6322         &omap44xx_l4_per__mmc5,
6323         &omap44xx_l3_main_2__mmu_ipu,
6324         &omap44xx_l4_cfg__mmu_dsp,
6325         &omap44xx_l3_main_2__ocmc_ram,
6326         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6327         &omap44xx_mpu_private__prcm_mpu,
6328         &omap44xx_l4_wkup__cm_core_aon,
6329         &omap44xx_l4_cfg__cm_core,
6330         &omap44xx_l4_wkup__prm,
6331         &omap44xx_l4_wkup__scrm,
6332         /* &omap44xx_l3_main_2__sl2if, */
6333         &omap44xx_l4_abe__slimbus1,
6334         &omap44xx_l4_abe__slimbus1_dma,
6335         &omap44xx_l4_per__slimbus2,
6336         &omap44xx_l4_cfg__smartreflex_core,
6337         &omap44xx_l4_cfg__smartreflex_iva,
6338         &omap44xx_l4_cfg__smartreflex_mpu,
6339         &omap44xx_l4_cfg__spinlock,
6340         &omap44xx_l4_wkup__timer1,
6341         &omap44xx_l4_per__timer2,
6342         &omap44xx_l4_per__timer3,
6343         &omap44xx_l4_per__timer4,
6344         &omap44xx_l4_abe__timer5,
6345         &omap44xx_l4_abe__timer5_dma,
6346         &omap44xx_l4_abe__timer6,
6347         &omap44xx_l4_abe__timer6_dma,
6348         &omap44xx_l4_abe__timer7,
6349         &omap44xx_l4_abe__timer7_dma,
6350         &omap44xx_l4_abe__timer8,
6351         &omap44xx_l4_abe__timer8_dma,
6352         &omap44xx_l4_per__timer9,
6353         &omap44xx_l4_per__timer10,
6354         &omap44xx_l4_per__timer11,
6355         &omap44xx_l4_per__uart1,
6356         &omap44xx_l4_per__uart2,
6357         &omap44xx_l4_per__uart3,
6358         &omap44xx_l4_per__uart4,
6359         /* &omap44xx_l4_cfg__usb_host_fs, */
6360         &omap44xx_l4_cfg__usb_host_hs,
6361         &omap44xx_l4_cfg__usb_otg_hs,
6362         &omap44xx_l4_cfg__usb_tll_hs,
6363         &omap44xx_l4_wkup__wd_timer2,
6364         &omap44xx_l4_abe__wd_timer3,
6365         &omap44xx_l4_abe__wd_timer3_dma,
6366         NULL,
6367 };
6368
6369 int __init omap44xx_hwmod_init(void)
6370 {
6371         omap_hwmod_init();
6372         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6373 }
6374