2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
6 * - known chipset handling
7 * - ACPI decoding and validation
9 * Per-architecture code takes care of the mappings and accesses
13 #include <linux/pci.h>
14 #include <linux/init.h>
15 #include <linux/acpi.h>
16 #include <linux/sfi_acpi.h>
17 #include <linux/bitmap.h>
18 #include <linux/dmi.h>
19 #include <linux/slab.h>
20 #include <linux/mutex.h>
21 #include <linux/rculist.h>
23 #include <asm/pci_x86.h>
26 #define PREFIX "PCI: "
28 /* Indicate if the mmcfg resources have been placed into the resource table. */
29 static int __initdata pci_mmcfg_resources_inserted;
30 static DEFINE_MUTEX(pci_mmcfg_lock);
32 LIST_HEAD(pci_mmcfg_list);
34 static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
37 release_resource(&cfg->res);
42 static __init void free_all_mmcfg(void)
44 struct pci_mmcfg_region *cfg, *tmp;
46 pci_mmcfg_arch_free();
47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
51 static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
53 struct pci_mmcfg_region *cfg;
55 /* keep list sorted by segment and starting bus number */
56 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
57 if (cfg->segment > new->segment ||
58 (cfg->segment == new->segment &&
59 cfg->start_bus >= new->start_bus)) {
60 list_add_tail_rcu(&new->list, &cfg->list);
64 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
67 static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
71 struct pci_mmcfg_region *new;
77 new = kzalloc(sizeof(*new), GFP_KERNEL);
82 new->segment = segment;
83 new->start_bus = start;
87 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
88 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
89 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
90 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
91 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
92 res->name = new->name;
94 printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
95 "%pR (base %#lx)\n", segment, start, end, &new->res,
96 (unsigned long) addr);
101 static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
104 struct pci_mmcfg_region *new;
106 new = pci_mmconfig_alloc(segment, start, end, addr);
108 mutex_lock(&pci_mmcfg_lock);
109 list_add_sorted(new);
110 mutex_unlock(&pci_mmcfg_lock);
116 struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
118 struct pci_mmcfg_region *cfg;
120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
128 static const char __init *pci_mmcfg_e7520(void)
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
134 if (win == 0x0000 || win == 0xf000)
137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
140 return "Intel Corporation E7520 Memory Controller Hub";
143 static const char __init *pci_mmcfg_intel_945(void)
145 u32 pciexbar, mask = 0, len = 0;
147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
154 switch ((pciexbar >> 1) & 3) {
171 /* Errata #2, things break when not aligned on a 256Mb boundary */
172 /* Can only happen in 64M/128M mode */
174 if ((pciexbar & mask) & 0x0fffffffU)
177 /* Don't hit the APIC registers and their friends */
178 if ((pciexbar & mask) >= 0xf0000000U)
181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
187 static const char __init *pci_mmcfg_amd_fam10h(void)
189 u32 low, high, address;
192 unsigned segnbits = 0, busnbits, end_bus;
194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
197 address = MSR_FAM10H_MMIO_CONF_BASE;
198 if (rdmsr_safe(address, &low, &high))
205 /* mmconfig is not enable */
206 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
209 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
211 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
212 FAM10H_MMIO_CONF_BUSRANGE_MASK;
215 * only handle bus 0 ?
222 segnbits = busnbits - 8;
226 end_bus = (1 << busnbits) - 1;
227 for (i = 0; i < (1 << segnbits); i++)
228 if (pci_mmconfig_add(i, 0, end_bus,
229 base + (1<<28) * i) == NULL) {
234 return "AMD Family 10h NB";
237 static bool __initdata mcp55_checked;
238 static const char __init *pci_mmcfg_nvidia_mcp55(void)
241 int mcp55_mmconf_found = 0;
243 static const u32 extcfg_regnum = 0x90;
244 static const u32 extcfg_regsize = 4;
245 static const u32 extcfg_enable_mask = 1<<31;
246 static const u32 extcfg_start_mask = 0xff<<16;
247 static const int extcfg_start_shift = 16;
248 static const u32 extcfg_size_mask = 0x3<<28;
249 static const int extcfg_size_shift = 28;
250 static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
251 static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
252 static const int extcfg_base_lshift = 25;
255 * do check if amd fam10h already took over
257 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
260 mcp55_checked = true;
261 for (bus = 0; bus < 256; bus++) {
265 int start, size_index, end;
267 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
269 device = (l >> 16) & 0xffff;
271 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
274 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
275 extcfg_regsize, &extcfg);
277 if (!(extcfg & extcfg_enable_mask))
280 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
281 base = extcfg & extcfg_base_mask[size_index];
282 /* base could > 4G */
283 base <<= extcfg_base_lshift;
284 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
285 end = start + extcfg_sizebus[size_index] - 1;
286 if (pci_mmconfig_add(0, start, end, base) == NULL)
288 mcp55_mmconf_found++;
291 if (!mcp55_mmconf_found)
294 return "nVidia MCP55";
297 struct pci_mmcfg_hostbridge_probe {
302 const char *(*probe)(void);
305 static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
306 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
307 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
308 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
309 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
310 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
311 0x1200, pci_mmcfg_amd_fam10h },
312 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
313 0x1200, pci_mmcfg_amd_fam10h },
314 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
315 0x0369, pci_mmcfg_nvidia_mcp55 },
318 static void __init pci_mmcfg_check_end_bus_number(void)
320 struct pci_mmcfg_region *cfg, *cfgx;
323 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
324 if (cfg->end_bus < cfg->start_bus)
327 /* Don't access the list head ! */
328 if (cfg->list.next == &pci_mmcfg_list)
331 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
332 if (cfg->end_bus >= cfgx->start_bus)
333 cfg->end_bus = cfgx->start_bus - 1;
337 static int __init pci_mmcfg_check_hostbridge(void)
350 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
351 bus = pci_mmcfg_probes[i].bus;
352 devfn = pci_mmcfg_probes[i].devfn;
353 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
355 device = (l >> 16) & 0xffff;
358 if (pci_mmcfg_probes[i].vendor == vendor &&
359 pci_mmcfg_probes[i].device == device)
360 name = pci_mmcfg_probes[i].probe();
363 printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
367 /* some end_bus_number is crazy, fix it */
368 pci_mmcfg_check_end_bus_number();
370 return !list_empty(&pci_mmcfg_list);
373 static void __init pci_mmcfg_insert_resources(void)
375 struct pci_mmcfg_region *cfg;
377 list_for_each_entry(cfg, &pci_mmcfg_list, list)
378 insert_resource(&iomem_resource, &cfg->res);
380 /* Mark that the resources have been inserted. */
381 pci_mmcfg_resources_inserted = 1;
384 static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
387 struct resource *mcfg_res = data;
388 struct acpi_resource_address64 address;
391 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
392 struct acpi_resource_fixed_memory32 *fixmem32 =
393 &res->data.fixed_memory32;
396 if ((mcfg_res->start >= fixmem32->address) &&
397 (mcfg_res->end < (fixmem32->address +
398 fixmem32->address_length))) {
400 return AE_CTRL_TERMINATE;
403 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
404 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
407 status = acpi_resource_to_address64(res, &address);
408 if (ACPI_FAILURE(status) ||
409 (address.address_length <= 0) ||
410 (address.resource_type != ACPI_MEMORY_RANGE))
413 if ((mcfg_res->start >= address.minimum) &&
414 (mcfg_res->end < (address.minimum + address.address_length))) {
416 return AE_CTRL_TERMINATE;
421 static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
422 void *context, void **rv)
424 struct resource *mcfg_res = context;
426 acpi_walk_resources(handle, METHOD_NAME__CRS,
427 check_mcfg_resource, context);
430 return AE_CTRL_TERMINATE;
435 static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
437 struct resource mcfg_res;
439 mcfg_res.start = start;
440 mcfg_res.end = end - 1;
443 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
446 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
449 return mcfg_res.flags;
452 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
454 static int __init is_mmconf_reserved(check_reserved_t is_reserved,
455 struct pci_mmcfg_region *cfg, int with_e820)
457 u64 addr = cfg->res.start;
458 u64 size = resource_size(&cfg->res);
460 int valid = 0, num_buses;
462 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
464 if (size < (16UL<<20))
468 if (size >= (16UL<<20) || size == old_size) {
469 printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
471 with_e820 ? "E820" : "ACPI motherboard resources");
474 if (old_size != size) {
476 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
477 num_buses = cfg->end_bus - cfg->start_bus + 1;
478 cfg->res.end = cfg->res.start +
479 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
480 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
481 "PCI MMCONFIG %04x [bus %02x-%02x]",
482 cfg->segment, cfg->start_bus, cfg->end_bus);
483 printk(KERN_INFO PREFIX
484 "MMCONFIG for %04x [bus%02x-%02x] "
485 "at %pR (base %#lx) (size reduced!)\n",
486 cfg->segment, cfg->start_bus, cfg->end_bus,
487 &cfg->res, (unsigned long) cfg->address);
494 static int __devinit pci_mmcfg_check_reserved(struct pci_mmcfg_region *cfg,
497 if (!early && !acpi_disabled) {
498 if (is_mmconf_reserved(is_acpi_reserved, cfg, 0))
501 printk(KERN_ERR FW_BUG PREFIX
502 "MMCONFIG at %pR not reserved in "
503 "ACPI motherboard resources\n",
507 /* Don't try to do this check unless configuration
508 type 1 is available. how about type 2 ?*/
510 return is_mmconf_reserved(e820_all_mapped, cfg, 1);
515 static void __init pci_mmcfg_reject_broken(int early)
517 struct pci_mmcfg_region *cfg;
519 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
520 if (pci_mmcfg_check_reserved(cfg, early) == 0) {
521 printk(KERN_INFO PREFIX "not using MMCONFIG\n");
528 static int __initdata known_bridge;
530 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
531 struct acpi_mcfg_allocation *cfg)
535 if (cfg->address < 0xFFFFFFFF)
538 if (!strcmp(mcfg->header.oem_id, "SGI") ||
539 !strcmp(mcfg->header.oem_id, "SGI2"))
542 if (mcfg->header.revision >= 1) {
543 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
548 printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
549 "is above 4GB, ignored\n", cfg->pci_segment,
550 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
554 static int __init pci_parse_mcfg(struct acpi_table_header *header)
556 struct acpi_table_mcfg *mcfg;
557 struct acpi_mcfg_allocation *cfg_table, *cfg;
564 mcfg = (struct acpi_table_mcfg *)header;
566 /* how many config structures do we have */
569 i = header->length - sizeof(struct acpi_table_mcfg);
570 while (i >= sizeof(struct acpi_mcfg_allocation)) {
572 i -= sizeof(struct acpi_mcfg_allocation);
575 printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
579 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
580 for (i = 0; i < entries; i++) {
582 if (acpi_mcfg_check_entry(mcfg, cfg)) {
587 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
588 cfg->end_bus_number, cfg->address) == NULL) {
589 printk(KERN_WARNING PREFIX
590 "no memory for MCFG entries\n");
599 static void __init __pci_mmcfg_init(int early)
601 /* MMCONFIG disabled */
602 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
605 /* MMCONFIG already enabled */
606 if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
609 /* for late to exit */
614 if (pci_mmcfg_check_hostbridge())
619 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
621 pci_mmcfg_reject_broken(early);
623 if (list_empty(&pci_mmcfg_list))
626 if (pcibios_last_bus < 0) {
627 const struct pci_mmcfg_region *cfg;
629 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
632 pcibios_last_bus = cfg->end_bus;
636 if (pci_mmcfg_arch_init())
637 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
640 * Signal not to attempt to insert mmcfg resources because
641 * the architecture mmcfg setup could not initialize.
643 pci_mmcfg_resources_inserted = 1;
647 void __init pci_mmcfg_early_init(void)
652 void __init pci_mmcfg_late_init(void)
657 static int __init pci_mmcfg_late_insert_resources(void)
660 * If resources are already inserted or we are not using MMCONFIG,
661 * don't insert the resources.
663 if ((pci_mmcfg_resources_inserted == 1) ||
664 (pci_probe & PCI_PROBE_MMCONF) == 0 ||
665 list_empty(&pci_mmcfg_list))
669 * Attempt to insert the mmcfg resources but not with the busy flag
670 * marked so it won't cause request errors when __request_region is
673 pci_mmcfg_insert_resources();
679 * Perform MMCONFIG resource insertion after PCI initialization to allow for
680 * misprogrammed MCFG tables that state larger sizes but actually conflict
681 * with other system resources.
683 late_initcall(pci_mmcfg_late_insert_resources);