2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
70 aips@50000000 { /* AIPS1 */
71 compatible = "fsl,aips-bus", "simple-bus";
74 reg = <0x50000000 0x10000000>;
78 compatible = "fsl,spba-bus", "simple-bus";
81 reg = <0x50000000 0x40000>;
84 esdhc@50004000 { /* ESDHC1 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50004000 0x4000>;
91 esdhc@50008000 { /* ESDHC2 */
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50008000 0x4000>;
98 uart3: serial@5000c000 {
99 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
100 reg = <0x5000c000 0x4000>;
105 ecspi@50010000 { /* ECSPI1 */
106 #address-cells = <1>;
108 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
109 reg = <0x50010000 0x4000>;
115 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
116 reg = <0x50014000 0x4000>;
118 fsl,fifo-depth = <15>;
119 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
123 esdhc@50020000 { /* ESDHC3 */
124 compatible = "fsl,imx53-esdhc";
125 reg = <0x50020000 0x4000>;
130 esdhc@50024000 { /* ESDHC4 */
131 compatible = "fsl,imx53-esdhc";
132 reg = <0x50024000 0x4000>;
138 gpio1: gpio@53f84000 {
139 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
140 reg = <0x53f84000 0x4000>;
141 interrupts = <50 51>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
148 gpio2: gpio@53f88000 {
149 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
150 reg = <0x53f88000 0x4000>;
151 interrupts = <52 53>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
158 gpio3: gpio@53f8c000 {
159 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
160 reg = <0x53f8c000 0x4000>;
161 interrupts = <54 55>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
168 gpio4: gpio@53f90000 {
169 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
170 reg = <0x53f90000 0x4000>;
171 interrupts = <56 57>;
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 wdog@53f98000 { /* WDOG1 */
179 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
180 reg = <0x53f98000 0x4000>;
185 wdog@53f9c000 { /* WDOG2 */
186 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
187 reg = <0x53f9c000 0x4000>;
192 uart1: serial@53fbc000 {
193 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
194 reg = <0x53fbc000 0x4000>;
199 uart2: serial@53fc0000 {
200 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
201 reg = <0x53fc0000 0x4000>;
207 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
208 reg = <0x53fc8000 0x4000>;
214 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
215 reg = <0x53fcc000 0x4000>;
220 gpio5: gpio@53fdc000 {
221 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
222 reg = <0x53fdc000 0x4000>;
223 interrupts = <103 104>;
226 interrupt-controller;
227 #interrupt-cells = <2>;
230 gpio6: gpio@53fe0000 {
231 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
232 reg = <0x53fe0000 0x4000>;
233 interrupts = <105 106>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
240 gpio7: gpio@53fe4000 {
241 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
242 reg = <0x53fe4000 0x4000>;
243 interrupts = <107 108>;
246 interrupt-controller;
247 #interrupt-cells = <2>;
250 i2c@53fec000 { /* I2C3 */
251 #address-cells = <1>;
253 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
254 reg = <0x53fec000 0x4000>;
259 uart4: serial@53ff0000 {
260 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
261 reg = <0x53ff0000 0x4000>;
267 aips@60000000 { /* AIPS2 */
268 compatible = "fsl,aips-bus", "simple-bus";
269 #address-cells = <1>;
271 reg = <0x60000000 0x10000000>;
274 uart5: serial@63f90000 {
275 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
276 reg = <0x63f90000 0x4000>;
281 ecspi@63fac000 { /* ECSPI2 */
282 #address-cells = <1>;
284 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
285 reg = <0x63fac000 0x4000>;
291 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
292 reg = <0x63fb0000 0x4000>;
297 #address-cells = <1>;
299 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
300 reg = <0x63fc0000 0x4000>;
305 i2c@63fc4000 { /* I2C2 */
306 #address-cells = <1>;
308 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
309 reg = <0x63fc4000 0x4000>;
314 i2c@63fc8000 { /* I2C1 */
315 #address-cells = <1>;
317 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
318 reg = <0x63fc8000 0x4000>;
324 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
325 reg = <0x63fcc000 0x4000>;
327 fsl,fifo-depth = <15>;
328 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
333 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
334 reg = <0x63fd0000 0x4000>;
339 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
340 reg = <0x63fe8000 0x4000>;
342 fsl,fifo-depth = <15>;
343 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
348 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
349 reg = <0x63fec000 0x4000>;