X-Git-Url: http://rtime.felk.cvut.cz/gitweb/arc.git/blobdiff_plain/79cf0308001e35225531aa542b87fda205b0ffaa..c030240a9c5b883baeb4a908c24bb14881830362:/arch/arm/arm_cr4/kernel/core_cr4.h

diff --git a/arch/arm/arm_cr4/kernel/core_cr4.h b/arch/arm/arm_cr4/kernel/core_cr4.h
index 51129059..d4e1a077 100644
--- a/arch/arm/arm_cr4/kernel/core_cr4.h
+++ b/arch/arm/arm_cr4/kernel/core_cr4.h
@@ -336,9 +336,9 @@ typedef volatile struct
 {
     uint32   CTL;
     uint32   SR;
-    unsigned     : 16;
-    unsigned REC :  8;
-    unsigned TEC :  8;
+    unsigned     : 16;	/* bits 31-16 - Reserved; 0x0008 - Error Counter Register */
+    unsigned REC :  8;	/* bits 15-8 - Receive Error Counter; 0x0008 - Error Counter Register */
+    unsigned TEC :  8;	/* bits 7-0 - Transmit Error Counter; 0x0008 - Error Counter Register */
     uint32   BTR;
     uint32   IR;
     uint32   TR;
@@ -387,7 +387,7 @@ typedef volatile struct
 	unsigned : 32;
     struct
     {
-        uint32   COM;
+        uint32   COM;		/* 0x0100: IF1 Command Register - Reserved, Command, Status, Msg Number */
         uint32   MASK;
         uint32   ARB;
         uint32   MC;
@@ -471,7 +471,17 @@ typedef volatile struct gioPort
     unsigned PSL;    /**< 0x001C: Pull Up/Down Selection Register */
 } GIO_RegisterType;
 
+/** @def GIO_PORTA_BASE
+*   @brief GIO Port (A) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTA
+*/
 #define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)
+/** @def GIO_PORTB_BASE
+*   @brief GIO Port (B) Register Pointer
+*
+*   Pointer used by the GIO driver to access PORTB
+*/
 #define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)
 #define GIO_HET_PORT1_BASE ((GIO_RegisterType *)0xFFF7B84CU)
 
@@ -482,20 +492,61 @@ typedef volatile struct gioPort
 */
 #define gioREG   ((GIO_Base_RegisterType *)0xFFF7BC00U)
 
-/** @def gioPORTA
-*   @brief GIO Port (A) Register Pointer
+
+/** @struct dmmBase
+*   @brief DMM Base Register Definition
 *
-*   Pointer used by the GIO driver to access PORTA
+*   This structure is used to access the DMM module egisters.
 */
-#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
-
-/** @def gioPORTB
-*   @brief GIO Port (B) Register Pointer
+/** @typedef dmmBASE_t
+*   @brief DMM Register Frame Type Definition
 *
-*   Pointer used by the GIO driver to access PORTB
+*   This type is used to access the DMM Registers.
 */
-#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
 
+typedef volatile struct dmmBase
+{
+    unsigned  GLBCTRL;    /**< 0x0000: Global control register 0         */
+    unsigned  INTSET;     /**< 0x0004: DMM Interrupt Set Register        */
+    unsigned  INTCLR;     /**< 0x0008: DMM Interrupt Clear Register      */
+    unsigned  INTLVL;     /**< 0x000C: DMM Interrupt Level Register      */
+    unsigned  INTFLG;     /**< 0x0010: DMM Interrupt Flag Register       */
+    unsigned  OFF1;       /**< 0x0014: DMM Interrupt Offset 1 Register           */
+    unsigned  OFF2;       /**< 0x0018: DMM Interrupt Offset 2 Register           */
+    unsigned  DDMDEST;    /**< 0x001C: DMM Direct Data Mode Destination Register                */
+    unsigned  DDMBL;      /**< 0x0020: DMM Direct Data Mode Blocksize Register           */
+    unsigned  DDMPT;      /**< 0x0024: DMM Direct Data Mode Pointer Register        */
+    unsigned  INTPT;      /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register     */
+    unsigned  DEST0REG1;  /**< 0x002C: DMM Destination 0 Region 1           */
+    unsigned  DEST0BL1;   /**< 0x0030: DMM Destination 0 Blocksize 1                     */
+    unsigned  DEST0REG2;  /**< 0x0034: DMM Destination 0 Region 2                  */
+    unsigned  DEST0BL2;   /**< 0x0038: DMM Destination 0 Blocksize 2                 */
+    unsigned  DEST1REG1;  /**< 0x003C: DMM Destination 1 Region 1                  */
+    unsigned  DEST1BL1;   /**< 0x0040: DMM Destination 1 Blocksize 1                 */
+    unsigned  DEST1REG2;  /**< 0x0044: DMM Destination 1 Region 2                   */
+    unsigned  DEST1BL2;   /**< 0x0048: DMM Destination 1 Blocksize 2                  */
+    unsigned  DEST2REG1;  /**< 0x004C: DMM Destination 2 Region 1                  */
+    unsigned  DEST2BL1;   /**< 0x0050: DMM Destination 2 Blocksize 1                  */
+    unsigned  DEST2REG2;  /**< 0x0054: DMM Destination 2 Region 2  */
+    unsigned  DEST2BL2;   /**< 0x0058: DMM Destination 2 Blocksize 2   */
+    unsigned  DEST3REG1;  /**< 0x005C: DMM Destination 3 Region 1 */
+    unsigned  DEST3BL1;   /**< 0x0060: DMM Destination 3 Blocksize 1                       */
+    unsigned  DEST3REG2;  /**< 0x0064: DMM Destination 3 Region 2              */
+    unsigned  DEST3BL2;   /**< 0x0068: DMM Destination 3 Blocksize 2              */
+    unsigned  PC0;        /**< 0x006C: DMM Pin Control 0                          */
+    unsigned  PC1;        /**< 0x0070: DMM Pin Control 1               */
+    unsigned  PC2;        /**< 0x0074: DMM Pin Control 2              */
+    unsigned  PC3;        /**< 0x0078: DMM Pin Control 3              */
+    unsigned  PC4;        /**< 0x007C: DMM Pin Control 4   */
+    unsigned  PC5;        /**< 0x0080: DMM Pin Control 5                 */
+    unsigned  PC6;        /**< 0x0084: DMM Pin Control 6                              */
+    unsigned  PC7;        /**< 0x0088: DMM Pin Control 7                             */
+    unsigned  PC8;        /**< 0x008C: DMM Pin Control 8                              */
+} DMM_Base_RegisterType;
+
+#define dmmReg ((DMM_Base_RegisterType *)0xFFFFF700U)
+
+#define GIO_DMM_PORT_BASE ((GIO_RegisterType *)0xFFFFF770U)
 
 typedef struct
 {