-/*\r
- * core_cr4.h\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
*\r
- * Created on: 12 okt 2010\r
- * Author: maek\r
- */\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
#ifndef CORE_CR4_H_\r
#define CORE_CR4_H_\r
{\r
uint32 CTL;\r
uint32 SR;\r
- unsigned : 16;\r
- unsigned REC : 8;\r
- unsigned TEC : 8;\r
+ unsigned : 16; /* bits 31-16 - Reserved; 0x0008 - Error Counter Register */\r
+ unsigned REC : 8; /* bits 15-8 - Receive Error Counter; 0x0008 - Error Counter Register */\r
+ unsigned TEC : 8; /* bits 7-0 - Transmit Error Counter; 0x0008 - Error Counter Register */\r
uint32 BTR;\r
uint32 IR;\r
uint32 TR;\r
unsigned : 32;\r
struct\r
{\r
- uint32 COM;\r
+ uint32 COM; /* 0x0100: IF1 Command Register - Reserved, Command, Status, Msg Number */\r
uint32 MASK;\r
uint32 ARB;\r
uint32 MC;\r
} Can_RegisterType;\r
\r
\r
-#define Can0_Base ((Can_RegisterType *)0xFFF7DC00)\r
-#define Can1_Base ((Can_RegisterType *)0xFFF7DE00)\r
+#define DCAN1_Base ((Can_RegisterType *)0xFFF7DC00)\r
+#define DCAN2_Base ((Can_RegisterType *)0xFFF7DE00)\r
+#define DCAN3_Base ((Can_RegisterType *)0xFFF7E000)\r
\r
\r
\r
unsigned FLG; /**< 0x0020: Interrupt Flag Register */\r
unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
-} gioBASE_t;\r
+} GIO_Base_RegisterType;\r
\r
\r
/** @struct gioPort\r
unsigned PDR; /**< 0x0014: Open Drain Regsiter */\r
unsigned PULDIS; /**< 0x0018: Pullup Disable Register */\r
unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
-} gioPORT_t;\r
+} GIO_RegisterType;\r
\r
+/** @def GIO_PORTA_BASE\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)\r
+/** @def GIO_PORTB_BASE\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)\r
+#define GIO_HET_PORT1_BASE ((GIO_RegisterType *)0xFFF7B84CU)\r
\r
/** @def gioREG\r
* @brief GIO Register Frame Pointer\r
*\r
* This pointer is used by the GIO driver to access the gio module registers.\r
*/\r
-#define gioREG ((gioBASE_t *)0xFFF7BC00U)\r
+#define gioREG ((GIO_Base_RegisterType *)0xFFF7BC00U)\r
\r
-/** @def gioPORTA\r
-* @brief GIO Port (A) Register Pointer\r
+\r
+/** @struct dmmBase\r
+* @brief DMM Base Register Definition\r
*\r
-* Pointer used by the GIO driver to access PORTA\r
+* This structure is used to access the DMM module egisters.\r
*/\r
-#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
-\r
-/** @def gioPORTB\r
-* @brief GIO Port (B) Register Pointer\r
+/** @typedef dmmBASE_t\r
+* @brief DMM Register Frame Type Definition\r
*\r
-* Pointer used by the GIO driver to access PORTB\r
+* This type is used to access the DMM Registers.\r
*/\r
-#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
\r
+typedef volatile struct dmmBase\r
+{\r
+ unsigned GLBCTRL; /**< 0x0000: Global control register 0 */\r
+ unsigned INTSET; /**< 0x0004: DMM Interrupt Set Register */\r
+ unsigned INTCLR; /**< 0x0008: DMM Interrupt Clear Register */\r
+ unsigned INTLVL; /**< 0x000C: DMM Interrupt Level Register */\r
+ unsigned INTFLG; /**< 0x0010: DMM Interrupt Flag Register */\r
+ unsigned OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */\r
+ unsigned OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */\r
+ unsigned DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */\r
+ unsigned DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */\r
+ unsigned DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */\r
+ unsigned INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */\r
+ unsigned DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */\r
+ unsigned DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */\r
+ unsigned DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */\r
+ unsigned DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */\r
+ unsigned DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */\r
+ unsigned DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */\r
+ unsigned DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */\r
+ unsigned DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */\r
+ unsigned DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */\r
+ unsigned DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */\r
+ unsigned DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */\r
+ unsigned DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */\r
+ unsigned DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */\r
+ unsigned DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */\r
+ unsigned DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */\r
+ unsigned DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */\r
+ unsigned PC0; /**< 0x006C: DMM Pin Control 0 */\r
+ unsigned PC1; /**< 0x0070: DMM Pin Control 1 */\r
+ unsigned PC2; /**< 0x0074: DMM Pin Control 2 */\r
+ unsigned PC3; /**< 0x0078: DMM Pin Control 3 */\r
+ unsigned PC4; /**< 0x007C: DMM Pin Control 4 */\r
+ unsigned PC5; /**< 0x0080: DMM Pin Control 5 */\r
+ unsigned PC6; /**< 0x0084: DMM Pin Control 6 */\r
+ unsigned PC7; /**< 0x0088: DMM Pin Control 7 */\r
+ unsigned PC8; /**< 0x008C: DMM Pin Control 8 */\r
+} DMM_Base_RegisterType;\r
+\r
+#define dmmReg ((DMM_Base_RegisterType *)0xFFFFF700U)\r
+\r
+#define GIO_DMM_PORT_BASE ((GIO_RegisterType *)0xFFFFF770U)\r
\r
typedef struct\r
{\r