+typedef volatile struct dmmBase\r
+{\r
+ unsigned GLBCTRL; /**< 0x0000: Global control register 0 */\r
+ unsigned INTSET; /**< 0x0004: DMM Interrupt Set Register */\r
+ unsigned INTCLR; /**< 0x0008: DMM Interrupt Clear Register */\r
+ unsigned INTLVL; /**< 0x000C: DMM Interrupt Level Register */\r
+ unsigned INTFLG; /**< 0x0010: DMM Interrupt Flag Register */\r
+ unsigned OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */\r
+ unsigned OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */\r
+ unsigned DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */\r
+ unsigned DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */\r
+ unsigned DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */\r
+ unsigned INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */\r
+ unsigned DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */\r
+ unsigned DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */\r
+ unsigned DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */\r
+ unsigned DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */\r
+ unsigned DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */\r
+ unsigned DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */\r
+ unsigned DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */\r
+ unsigned DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */\r
+ unsigned DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */\r
+ unsigned DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */\r
+ unsigned DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */\r
+ unsigned DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */\r
+ unsigned DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */\r
+ unsigned DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */\r
+ unsigned DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */\r
+ unsigned DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */\r
+ unsigned PC0; /**< 0x006C: DMM Pin Control 0 */\r
+ unsigned PC1; /**< 0x0070: DMM Pin Control 1 */\r
+ unsigned PC2; /**< 0x0074: DMM Pin Control 2 */\r
+ unsigned PC3; /**< 0x0078: DMM Pin Control 3 */\r
+ unsigned PC4; /**< 0x007C: DMM Pin Control 4 */\r
+ unsigned PC5; /**< 0x0080: DMM Pin Control 5 */\r
+ unsigned PC6; /**< 0x0084: DMM Pin Control 6 */\r
+ unsigned PC7; /**< 0x0088: DMM Pin Control 7 */\r
+ unsigned PC8; /**< 0x008C: DMM Pin Control 8 */\r
+} DMM_Base_RegisterType;\r
+\r
+#define dmmReg ((DMM_Base_RegisterType *)0xFFFFF700U)\r
+\r
+#define GIO_DMM_PORT_BASE ((GIO_RegisterType *)0xFFFFF770U)\r