-
+\r
/**************************************************************************/\r
/* FILE NAME: mpc5567.h COPYRIGHT (c) Freescale 2007 */\r
/* VERSION: 1.6 All Rights Reserved */\r
#ifndef _MPC5567_H_\r
#define _MPC5567_H_\r
\r
+#include "Compiler.h"\r
#include "typedefs.h"\r
\r
#ifdef __cplusplus\r
/****************************************************************************/\r
/* MODULE : PBRIDGE_A Peripheral Bridge */\r
/****************************************************************************/\r
- struct PBRIDGE_A_tag {\r
+ CC_EXTENSION struct PBRIDGE_A_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : PBRIDGE_B Peripheral Bridge */\r
/****************************************************************************/\r
- struct PBRIDGE_B_tag {\r
+ CC_EXTENSION struct PBRIDGE_B_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FMPLL */\r
/****************************************************************************/\r
- struct FMPLL_tag {\r
+ CC_EXTENSION struct FMPLL_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : External Bus Interface (EBI) */\r
/****************************************************************************/\r
- struct CS_tag {\r
+ CC_EXTENSION struct CS_tag {\r
union { /* Base Register Bank */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FLASH */\r
/****************************************************************************/\r
- struct FLASH_tag {\r
+ CC_EXTENSION struct FLASH_tag {\r
union { /* Module Configuration Register */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : SIU */\r
/****************************************************************************/\r
- struct SIU_tag {\r
+ CC_EXTENSION struct SIU_tag {\r
int32_t SIU_reserved0;\r
\r
union { /* MCU ID Register */\r
/****************************************************************************/\r
/* MODULE : EMIOS */\r
/****************************************************************************/\r
- struct EMIOS_tag {\r
+ CC_EXTENSION struct EMIOS_tag {\r
union {\r
vuint32_t R;\r
struct {\r
\r
/***************************Configuration Registers**************************/\r
\r
- struct ETPU_tag {\r
+ CC_EXTENSION struct ETPU_tag {\r
union { /* MODULE CONFIGURATION REGISTER */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : XBAR CrossBar */\r
/****************************************************************************/\r
- struct XBAR_tag {\r
+ CC_EXTENSION struct XBAR_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : ECSM */\r
/****************************************************************************/\r
- struct ECSM_tag {\r
+ CC_EXTENSION struct ECSM_tag {\r
\r
uint32_t ecsm_reserved1[5];\r
\r
/****************************************************************************/\r
/* MODULE : eDMA */\r
/****************************************************************************/\r
- struct EDMA_tag {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t GRP3PRI:2;\r
- vuint32_t GRP2PRI:2;\r
- vuint32_t GRP1PRI:2;\r
- vuint32_t GRP0PRI:2;\r
- vuint32_t:4;\r
- vuint32_t ERGA:1;\r
- vuint32_t ERCA:1;\r
- vuint32_t EDBG:1;\r
- vuint32_t EBW:1;\r
- } B;\r
- } CR; /* Control Register */\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t VLD:1;\r
- vuint32_t:15;\r
- vuint32_t GPE:1;\r
- vuint32_t CPE:1;\r
- vuint32_t ERRCHN:6;\r
- vuint32_t SAE:1;\r
- vuint32_t SOE:1;\r
- vuint32_t DAE:1;\r
- vuint32_t DOE:1;\r
- vuint32_t NCE:1;\r
- vuint32_t SGE:1;\r
- vuint32_t SBE:1;\r
- vuint32_t DBE:1;\r
- } B;\r
- } ESR; /* Error Status Register */\r
- uint32_t edma_reserved_erqrh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t ERQ31:1;\r
- vuint32_t ERQ30:1;\r
- vuint32_t ERQ29:1;\r
- vuint32_t ERQ28:1;\r
- vuint32_t ERQ27:1;\r
- vuint32_t ERQ26:1;\r
- vuint32_t ERQ25:1;\r
- vuint32_t ERQ24:1;\r
- vuint32_t ERQ23:1;\r
- vuint32_t ERQ22:1;\r
- vuint32_t ERQ21:1;\r
- vuint32_t ERQ20:1;\r
- vuint32_t ERQ19:1;\r
- vuint32_t ERQ18:1;\r
- vuint32_t ERQ17:1;\r
- vuint32_t ERQ16:1;\r
- vuint32_t ERQ15:1;\r
- vuint32_t ERQ14:1;\r
- vuint32_t ERQ13:1;\r
- vuint32_t ERQ12:1;\r
- vuint32_t ERQ11:1;\r
- vuint32_t ERQ10:1;\r
- vuint32_t ERQ09:1;\r
- vuint32_t ERQ08:1;\r
- vuint32_t ERQ07:1;\r
- vuint32_t ERQ06:1;\r
- vuint32_t ERQ05:1;\r
- vuint32_t ERQ04:1;\r
- vuint32_t ERQ03:1;\r
- vuint32_t ERQ02:1;\r
- vuint32_t ERQ01:1;\r
- vuint32_t ERQ00:1;\r
- } B;\r
- } ERQRL; /* DMA Enable Request Register Low */\r
- uint32_t edma_reserved_eeirh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t EEI31:1;\r
- vuint32_t EEI30:1;\r
- vuint32_t EEI29:1;\r
- vuint32_t EEI28:1;\r
- vuint32_t EEI27:1;\r
- vuint32_t EEI26:1;\r
- vuint32_t EEI25:1;\r
- vuint32_t EEI24:1;\r
- vuint32_t EEI23:1;\r
- vuint32_t EEI22:1;\r
- vuint32_t EEI21:1;\r
- vuint32_t EEI20:1;\r
- vuint32_t EEI19:1;\r
- vuint32_t EEI18:1;\r
- vuint32_t EEI17:1;\r
- vuint32_t EEI16:1;\r
- vuint32_t EEI15:1;\r
- vuint32_t EEI14:1;\r
- vuint32_t EEI13:1;\r
- vuint32_t EEI12:1;\r
- vuint32_t EEI11:1;\r
- vuint32_t EEI10:1;\r
- vuint32_t EEI09:1;\r
- vuint32_t EEI08:1;\r
- vuint32_t EEI07:1;\r
- vuint32_t EEI06:1;\r
- vuint32_t EEI05:1;\r
- vuint32_t EEI04:1;\r
- vuint32_t EEI03:1;\r
- vuint32_t EEI02:1;\r
- vuint32_t EEI01:1;\r
- vuint32_t EEI00:1;\r
- } B;\r
- } EEIRL; /* DMA Enable Error Interrupt Register Low */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SERQR; /* DMA Set Enable Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CERQR; /* DMA Clear Enable Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SEEIR; /* DMA Set Enable Error Interrupt Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CEEIR; /* DMA Clear Enable Error Interrupt Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CIRQR; /* DMA Clear Interrupt Request Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CER; /* DMA Clear error Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } SSBR; /* Set Start Bit Register */\r
- union {\r
- vuint8_t R;\r
- vuint8_t B;\r
- } CDSBR; /* Clear Done Status Bit Register */\r
- uint32_t edma_reserved_irqrh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t INT31:1;\r
- vuint32_t INT30:1;\r
- vuint32_t INT29:1;\r
- vuint32_t INT28:1;\r
- vuint32_t INT27:1;\r
- vuint32_t INT26:1;\r
- vuint32_t INT25:1;\r
- vuint32_t INT24:1;\r
- vuint32_t INT23:1;\r
- vuint32_t INT22:1;\r
- vuint32_t INT21:1;\r
- vuint32_t INT20:1;\r
- vuint32_t INT19:1;\r
- vuint32_t INT18:1;\r
- vuint32_t INT17:1;\r
- vuint32_t INT16:1;\r
- vuint32_t INT15:1;\r
- vuint32_t INT14:1;\r
- vuint32_t INT13:1;\r
- vuint32_t INT12:1;\r
- vuint32_t INT11:1;\r
- vuint32_t INT10:1;\r
- vuint32_t INT09:1;\r
- vuint32_t INT08:1;\r
- vuint32_t INT07:1;\r
- vuint32_t INT06:1;\r
- vuint32_t INT05:1;\r
- vuint32_t INT04:1;\r
- vuint32_t INT03:1;\r
- vuint32_t INT02:1;\r
- vuint32_t INT01:1;\r
- vuint32_t INT00:1;\r
- } B;\r
- } IRQRL; /* DMA Interrupt Request Low */\r
- uint32_t edma_reserved_erh;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t ERR31:1;\r
- vuint32_t ERR30:1;\r
- vuint32_t ERR29:1;\r
- vuint32_t ERR28:1;\r
- vuint32_t ERR27:1;\r
- vuint32_t ERR26:1;\r
- vuint32_t ERR25:1;\r
- vuint32_t ERR24:1;\r
- vuint32_t ERR23:1;\r
- vuint32_t ERR22:1;\r
- vuint32_t ERR21:1;\r
- vuint32_t ERR20:1;\r
- vuint32_t ERR19:1;\r
- vuint32_t ERR18:1;\r
- vuint32_t ERR17:1;\r
- vuint32_t ERR16:1;\r
- vuint32_t ERR15:1;\r
- vuint32_t ERR14:1;\r
- vuint32_t ERR13:1;\r
- vuint32_t ERR12:1;\r
- vuint32_t ERR11:1;\r
- vuint32_t ERR10:1;\r
- vuint32_t ERR09:1;\r
- vuint32_t ERR08:1;\r
- vuint32_t ERR07:1;\r
- vuint32_t ERR06:1;\r
- vuint32_t ERR05:1;\r
- vuint32_t ERR04:1;\r
- vuint32_t ERR03:1;\r
- vuint32_t ERR02:1;\r
- vuint32_t ERR01:1;\r
- vuint32_t ERR00:1;\r
- } B;\r
- } ERL; /* DMA Error Low */\r
- uint32_t edma_reserved1[52];\r
-\r
- union {\r
- vuint8_t R;\r
- struct {\r
- vuint8_t ECP:1;\r
-\r
- vuint8_t:1;\r
- vuint8_t GRPPRI:2;\r
- vuint8_t CHPRI:4;\r
-\r
- } B;\r
- } CPR[64]; /* Channel n Priority */\r
-\r
- uint32_t edma_reserved2[944];\r
-\r
-/****************************************************************************/\r
-/* DMA2 Transfer Control Descriptor */\r
-/****************************************************************************/\r
-\r
- struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
- vuint32_t SADDR; /* source address */\r
-\r
- vuint16_t SMOD:5; /* source address modulo */\r
- vuint16_t SSIZE:3; /* source transfer size */\r
- vuint16_t DMOD:5; /* destination address modulo */\r
- vuint16_t DSIZE:3; /* destination transfer size */\r
- vint16_t SOFF; /* signed source address offset */\r
-\r
- vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
-\r
- vint32_t SLAST; /* last destination address adjustment, or\r
-\r
- scatter/gather address (if e_sg = 1) */\r
- vuint32_t DADDR; /* destination address */\r
-\r
- vuint16_t CITERE_LINK:1;\r
- vuint16_t CITER:15;\r
-\r
- vint16_t DOFF; /* signed destination address offset */\r
-\r
- vint32_t DLAST_SGA;\r
-\r
- vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */\r
- vuint16_t BITER:15;\r
-\r
- vuint16_t BWC:2; /* bandwidth control */\r
- vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
- vuint16_t DONE:1; /* channel done */\r
- vuint16_t ACTIVE:1; /* channel active */\r
- vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
- vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
- vuint16_t D_REQ:1; /* disable ipd_req when done */\r
- vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
- vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
- vuint16_t START:1; /* explicit channel start */\r
- } TCD[64]; /* transfer_control_descriptor */\r
-\r
- };\r
-\r
- struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
-\r
- struct tcd_alt1_t {\r
- vuint32_t SADDR; /* source address */\r
-\r
- vuint16_t SMOD:5; /* source address modulo */\r
- vuint16_t SSIZE:3; /* source transfer size */\r
- vuint16_t DMOD:5; /* destination address modulo */\r
- vuint16_t DSIZE:3; /* destination transfer size */\r
- vint16_t SOFF; /* signed source address offset */\r
-\r
- vuint32_t NBYTES; /* inner (\93minor\94) byte count */\r
-\r
- vint32_t SLAST; /* last destination address adjustment, or\r
-\r
- scatter/gather address (if e_sg = 1) */\r
- vuint32_t DADDR; /* destination address */\r
+#include "ip_edma.h"\r
\r
- vuint16_t CITERE_LINK:1;\r
- vuint16_t CITERLINKCH:6;\r
- vuint16_t CITER:9;\r
-\r
- vint16_t DOFF; /* signed destination address offset */\r
-\r
- vint32_t DLAST_SGA;\r
-\r
- vuint16_t BITERE_LINK:1; /* beginning (\93major\94) iteration count */\r
- vuint16_t BITERLINKCH:6;\r
- vuint16_t BITER:9;\r
-\r
- vuint16_t BWC:2; /* bandwidth control */\r
- vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */\r
- vuint16_t DONE:1; /* channel done */\r
- vuint16_t ACTIVE:1; /* channel active */\r
- vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */\r
- vuint16_t E_SG:1; /* enable scatter/gather descriptor */\r
- vuint16_t D_REQ:1; /* disable ipd_req when done */\r
- vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */\r
- vuint16_t INT_MAJ:1; /* interrupt on major loop completion */\r
- vuint16_t START:1; /* explicit channel start */\r
- } TCD[64]; /* transfer_control_descriptor */\r
- };\r
/****************************************************************************/\r
/* MODULE : INTC */\r
/****************************************************************************/\r
- struct INTC_tag {\r
+ CC_EXTENSION struct INTC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : EQADC */\r
/****************************************************************************/\r
- struct EQADC_tag {\r
+ CC_EXTENSION struct EQADC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : eSCI */\r
/****************************************************************************/\r
- struct ESCI_tag {\r
+ CC_EXTENSION struct ESCI_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FlexCAN */\r
/****************************************************************************/\r
- struct FLEXCAN2_tag {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t MDIS:1;\r
- vuint32_t FRZ:1;\r
- vuint32_t:1;\r
- vuint32_t HALT:1;\r
- vuint32_t NOTRDY:1;\r
- vuint32_t:1;\r
- vuint32_t SOFTRST:1;\r
- vuint32_t FRZACK:1;\r
- vuint32_t:1;\r
- vuint32_t:1;\r
-\r
- vuint32_t WRNEN:1;\r
-\r
- vuint32_t MDISACK:1;\r
- vuint32_t:1;\r
- vuint32_t:1;\r
-\r
- vuint32_t SRXDIS:1;\r
- vuint32_t MBFEN:1;\r
- vuint32_t:10;\r
-\r
- vuint32_t MAXMB:6;\r
- } B;\r
- } MCR; /* Module Configuration Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t PRESDIV:8;\r
- vuint32_t RJW:2;\r
- vuint32_t PSEG1:3;\r
- vuint32_t PSEG2:3;\r
- vuint32_t BOFFMSK:1;\r
- vuint32_t ERRMSK:1;\r
- vuint32_t CLKSRC:1;\r
- vuint32_t LPB:1;\r
-\r
- vuint32_t TWRNMSK:1;\r
- vuint32_t RWRNMSK:1;\r
- vuint32_t:2;\r
-\r
- vuint32_t SMP:1;\r
- vuint32_t BOFFREC:1;\r
- vuint32_t TSYN:1;\r
- vuint32_t LBUF:1;\r
- vuint32_t LOM:1;\r
- vuint32_t PROPSEG:3;\r
- } B;\r
- } CR; /* Control Register */\r
-\r
- union {\r
- vuint32_t R;\r
- } TIMER; /* Free Running Timer */\r
- int32_t FLEXCAN_reserved00;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RXGMASK; /* RX Global Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RX14MASK; /* RX 14 Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RX15MASK; /* RX 15 Mask */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:16;\r
- vuint32_t RXECNT:8;\r
- vuint32_t TXECNT:8;\r
- } B;\r
- } ECR; /* Error Counter Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:14;\r
-\r
- vuint32_t TWRNINT:1;\r
- vuint32_t RWRNINT:1;\r
-\r
- vuint32_t BIT1ERR:1;\r
- vuint32_t BIT0ERR:1;\r
- vuint32_t ACKERR:1;\r
- vuint32_t CRCERR:1;\r
- vuint32_t FRMERR:1;\r
- vuint32_t STFERR:1;\r
- vuint32_t TXWRN:1;\r
- vuint32_t RXWRN:1;\r
- vuint32_t IDLE:1;\r
- vuint32_t TXRX:1;\r
- vuint32_t FLTCONF:2;\r
- vuint32_t:1;\r
- vuint32_t BOFFINT:1;\r
- vuint32_t ERRINT:1;\r
- vuint32_t:1;\r
- } B;\r
- } ESR; /* Error and Status Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF63M:1;\r
- vuint32_t BUF62M:1;\r
- vuint32_t BUF61M:1;\r
- vuint32_t BUF60M:1;\r
- vuint32_t BUF59M:1;\r
- vuint32_t BUF58M:1;\r
- vuint32_t BUF57M:1;\r
- vuint32_t BUF56M:1;\r
- vuint32_t BUF55M:1;\r
- vuint32_t BUF54M:1;\r
- vuint32_t BUF53M:1;\r
- vuint32_t BUF52M:1;\r
- vuint32_t BUF51M:1;\r
- vuint32_t BUF50M:1;\r
- vuint32_t BUF49M:1;\r
- vuint32_t BUF48M:1;\r
- vuint32_t BUF47M:1;\r
- vuint32_t BUF46M:1;\r
- vuint32_t BUF45M:1;\r
- vuint32_t BUF44M:1;\r
- vuint32_t BUF43M:1;\r
- vuint32_t BUF42M:1;\r
- vuint32_t BUF41M:1;\r
- vuint32_t BUF40M:1;\r
- vuint32_t BUF39M:1;\r
- vuint32_t BUF38M:1;\r
- vuint32_t BUF37M:1;\r
- vuint32_t BUF36M:1;\r
- vuint32_t BUF35M:1;\r
- vuint32_t BUF34M:1;\r
- vuint32_t BUF33M:1;\r
- vuint32_t BUF32M:1;\r
- } B;\r
- } IMRH; /* Interruput Masks Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF31M:1;\r
- vuint32_t BUF30M:1;\r
- vuint32_t BUF29M:1;\r
- vuint32_t BUF28M:1;\r
- vuint32_t BUF27M:1;\r
- vuint32_t BUF26M:1;\r
- vuint32_t BUF25M:1;\r
- vuint32_t BUF24M:1;\r
- vuint32_t BUF23M:1;\r
- vuint32_t BUF22M:1;\r
- vuint32_t BUF21M:1;\r
- vuint32_t BUF20M:1;\r
- vuint32_t BUF19M:1;\r
- vuint32_t BUF18M:1;\r
- vuint32_t BUF17M:1;\r
- vuint32_t BUF16M:1;\r
- vuint32_t BUF15M:1;\r
- vuint32_t BUF14M:1;\r
- vuint32_t BUF13M:1;\r
- vuint32_t BUF12M:1;\r
- vuint32_t BUF11M:1;\r
- vuint32_t BUF10M:1;\r
- vuint32_t BUF09M:1;\r
- vuint32_t BUF08M:1;\r
- vuint32_t BUF07M:1;\r
- vuint32_t BUF06M:1;\r
- vuint32_t BUF05M:1;\r
- vuint32_t BUF04M:1;\r
- vuint32_t BUF03M:1;\r
- vuint32_t BUF02M:1;\r
- vuint32_t BUF01M:1;\r
- vuint32_t BUF00M:1;\r
- } B;\r
- } IMRL; /* Interruput Masks Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF63I:1;\r
- vuint32_t BUF62I:1;\r
- vuint32_t BUF61I:1;\r
- vuint32_t BUF60I:1;\r
- vuint32_t BUF59I:1;\r
- vuint32_t BUF58I:1;\r
- vuint32_t BUF57I:1;\r
- vuint32_t BUF56I:1;\r
- vuint32_t BUF55I:1;\r
- vuint32_t BUF54I:1;\r
- vuint32_t BUF53I:1;\r
- vuint32_t BUF52I:1;\r
- vuint32_t BUF51I:1;\r
- vuint32_t BUF50I:1;\r
- vuint32_t BUF49I:1;\r
- vuint32_t BUF48I:1;\r
- vuint32_t BUF47I:1;\r
- vuint32_t BUF46I:1;\r
- vuint32_t BUF45I:1;\r
- vuint32_t BUF44I:1;\r
- vuint32_t BUF43I:1;\r
- vuint32_t BUF42I:1;\r
- vuint32_t BUF41I:1;\r
- vuint32_t BUF40I:1;\r
- vuint32_t BUF39I:1;\r
- vuint32_t BUF38I:1;\r
- vuint32_t BUF37I:1;\r
- vuint32_t BUF36I:1;\r
- vuint32_t BUF35I:1;\r
- vuint32_t BUF34I:1;\r
- vuint32_t BUF33I:1;\r
- vuint32_t BUF32I:1;\r
- } B;\r
- } IFRH; /* Interruput Flag Register */\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t BUF31I:1;\r
- vuint32_t BUF30I:1;\r
- vuint32_t BUF29I:1;\r
- vuint32_t BUF28I:1;\r
- vuint32_t BUF27I:1;\r
- vuint32_t BUF26I:1;\r
- vuint32_t BUF25I:1;\r
- vuint32_t BUF24I:1;\r
- vuint32_t BUF23I:1;\r
- vuint32_t BUF22I:1;\r
- vuint32_t BUF21I:1;\r
- vuint32_t BUF20I:1;\r
- vuint32_t BUF19I:1;\r
- vuint32_t BUF18I:1;\r
- vuint32_t BUF17I:1;\r
- vuint32_t BUF16I:1;\r
- vuint32_t BUF15I:1;\r
- vuint32_t BUF14I:1;\r
- vuint32_t BUF13I:1;\r
- vuint32_t BUF12I:1;\r
- vuint32_t BUF11I:1;\r
- vuint32_t BUF10I:1;\r
- vuint32_t BUF09I:1;\r
- vuint32_t BUF08I:1;\r
- vuint32_t BUF07I:1;\r
- vuint32_t BUF06I:1;\r
- vuint32_t BUF05I:1;\r
- vuint32_t BUF04I:1;\r
- vuint32_t BUF03I:1;\r
- vuint32_t BUF02I:1;\r
- vuint32_t BUF01I:1;\r
- vuint32_t BUF00I:1;\r
- } B;\r
- } IFRL; /* Interruput Flag Register */\r
-\r
- uint32_t flexcan2_reserved2[19];\r
-\r
- struct canbuf_t {\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:4;\r
- vuint32_t CODE:4;\r
- vuint32_t:1;\r
- vuint32_t SRR:1;\r
- vuint32_t IDE:1;\r
- vuint32_t RTR:1;\r
- vuint32_t LENGTH:4;\r
- vuint32_t TIMESTAMP:16;\r
- } B;\r
- } CS;\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t STD_ID:11;\r
- vuint32_t EXT_ID:18;\r
- } B;\r
- } ID;\r
-\r
- union {\r
- vuint8_t B[8]; /* Data buffer in Bytes (8 bits) */\r
- vuint16_t H[4]; /* Data buffer in Half-words (16 bits) */\r
- vuint32_t W[2]; /* Data buffer in words (32 bits) */\r
- vuint32_t R[2]; /* Data buffer in words (32 bits) */\r
- } DATA;\r
-\r
- } BUF[64];\r
-\r
- uint32_t flexcan2_reserved3[256];\r
-\r
- union {\r
- vuint32_t R;\r
- struct {\r
- vuint32_t:3;\r
- vuint32_t MI:29;\r
- } B;\r
- } RXIMR[64]; /* RX Individual Mask Registers */\r
-\r
- };\r
+#include "ip_flexcan.h"\r
/****************************************************************************/\r
/* MODULE : FEC */\r
/****************************************************************************/\r
- struct FEC_tag {\r
+ CC_EXTENSION struct FEC_tag {\r
\r
uint32_t fec_reserved_start[0x1];\r
\r
/* MODULE : FlexRay */\r
/****************************************************************************/\r
\r
- typedef union uMVR {\r
+ CC_EXTENSION typedef union uMVR {\r
vuint16_t R;\r
struct {\r
vuint16_t CHIVER:8; /* CHI Version Number */\r
} B;\r
} MVR_t;\r
\r
- typedef union uMCR {\r
+ CC_EXTENSION typedef union uMCR {\r
vuint16_t R;\r
struct {\r
vuint16_t MEN:1; /* module enable */\r
vuint16_t:1;\r
} B;\r
} MCR_t;\r
- typedef union uSTBSCR {\r
+ CC_EXTENSION typedef union uSTBSCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STBPSEL:2; /* strobe port select */\r
} B;\r
} STBSCR_t;\r
- typedef union uSTBPCR {\r
+ CC_EXTENSION typedef union uSTBPCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} STBPCR_t;\r
\r
- typedef union uMBDSR {\r
+ CC_EXTENSION typedef union uMBDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */\r
} B;\r
} MBDSR_t;\r
- typedef union uMBSSUTR {\r
+ CC_EXTENSION typedef union uMBSSUTR {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBSSUTR_t;\r
\r
- typedef union uPOCR {\r
+ CC_EXTENSION typedef union uPOCR {\r
vuint16_t R;\r
vuint8_t byte[2];\r
struct {\r
} B;\r
} POCR_t;\r
/* protocol commands */\r
- typedef union uGIFER {\r
+ CC_EXTENSION typedef union uGIFER {\r
vuint16_t R;\r
struct {\r
vuint16_t MIF:1; /* module interrupt flag */\r
vuint16_t TBIE:1; /* transmit buffer interrupt enable */\r
} B;\r
} GIFER_t;\r
- typedef union uPIFR0 {\r
+ CC_EXTENSION typedef union uPIFR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */\r
vuint16_t CYSIF:1; /* cycle start interrupt flag */\r
} B;\r
} PIFR0_t;\r
- typedef union uPIFR1 {\r
+ CC_EXTENSION typedef union uPIFR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIF:1; /* error mode changed interrupt flag */\r
vuint16_t:4;\r
} B;\r
} PIFR1_t;\r
- typedef union uPIER0 {\r
+ CC_EXTENSION typedef union uPIER0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */\r
vuint16_t CYSIE:1; /* cycle start interrupt enable */\r
} B;\r
} PIER0_t;\r
- typedef union uPIER1 {\r
+ CC_EXTENSION typedef union uPIER1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIE:1; /* error mode changed interrupt enable */\r
vuint16_t:4;\r
} B;\r
} PIER1_t;\r
- typedef union uCHIERFR {\r
+ CC_EXTENSION typedef union uCHIERFR {\r
vuint16_t R;\r
struct {\r
vuint16_t FRLBEF:1; /* flame lost channel B error flag */\r
vuint16_t ILSAEF:1; /* illegal access error flag */\r
} B;\r
} CHIERFR_t;\r
- typedef union uMBIVEC {\r
+ CC_EXTENSION typedef union uMBIVEC {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBIVEC_t;\r
\r
- typedef union uPSR0 {\r
+ CC_EXTENSION typedef union uPSR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ERRMODE:2; /* error mode */\r
/* protocol states */\r
/* protocol sub-states */\r
/* wakeup status */\r
- typedef union uPSR1 {\r
+ CC_EXTENSION typedef union uPSR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t CSAA:1; /* cold start attempt abort flag */\r
vuint16_t APTAC:5; /* allow passive to active counter */\r
} B;\r
} PSR1_t;\r
- typedef union uPSR2 {\r
+ CC_EXTENSION typedef union uPSR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t NBVB:1; /* NIT boundary violation on channel B */\r
vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */\r
} B;\r
} PSR2_t;\r
- typedef union uPSR3 {\r
+ CC_EXTENSION typedef union uPSR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
vuint16_t AVFA:1; /* aggregated valid frame on channel A */\r
} B;\r
} PSR3_t;\r
- typedef union uCIFRR {\r
+ CC_EXTENSION typedef union uCIFRR {\r
vuint16_t R;\r
struct {\r
vuint16_t:8;\r
vuint16_t TBIFR:1; /* transmit buffer interrupt flag */\r
} B;\r
} CIFRR_t;\r
- typedef union uSFCNTR {\r
+ CC_EXTENSION typedef union uSFCNTR {\r
vuint16_t R;\r
struct {\r
vuint16_t SFEVB:4; /* sync frames channel B, even cycle */\r
} B;\r
} SFCNTR_t;\r
\r
- typedef union uSFTCCSR {\r
+ CC_EXTENSION typedef union uSFTCCSR {\r
vuint16_t R;\r
struct {\r
vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */\r
vuint16_t SIDEN:1; /* sync frame ID table enable */\r
} B;\r
} SFTCCSR_t;\r
- typedef union uSFIDRFR {\r
+ CC_EXTENSION typedef union uSFIDRFR {\r
vuint16_t R;\r
struct {\r
vuint16_t:6;\r
} B;\r
} SFIDRFR_t;\r
\r
- typedef union uTICCR {\r
+ CC_EXTENSION typedef union uTICCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
\r
} B;\r
} TICCR_t;\r
- typedef union uTI1CYSR {\r
+ CC_EXTENSION typedef union uTI1CYSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} TI1CYSR_t;\r
\r
- typedef union uSSSR {\r
+ CC_EXTENSION typedef union uSSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} SSSR_t;\r
\r
- typedef union uSSCCR {\r
+ CC_EXTENSION typedef union uSSCCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STATUSMASK:4; /* slot status mask */\r
} B;\r
} SSCCR_t;\r
- typedef union uSSR {\r
+ CC_EXTENSION typedef union uSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t VFB:1; /* valid frame on channel B */\r
vuint16_t TCA:1; /* tx conflict on channel A */\r
} B;\r
} SSR_t;\r
- typedef union uMTSCFR {\r
+ CC_EXTENSION typedef union uMTSCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t MTE:1; /* media access test symbol transmission enable */\r
vuint16_t CYCCNTVAL:6; /* cycle counter value */\r
} B;\r
} MTSCFR_t;\r
- typedef union uRSBIR {\r
+ CC_EXTENSION typedef union uRSBIR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t RSBIDX:8; /* receive shadow buffer index */\r
} B;\r
} RSBIR_t;\r
- typedef union uRFDSR {\r
+ CC_EXTENSION typedef union uRFDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t FIFODEPTH:8; /* fifo depth */\r
} B;\r
} RFDSR_t;\r
\r
- typedef union uRFRFCFR {\r
+ CC_EXTENSION typedef union uRFRFCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} RFRFCFR_t;\r
\r
- typedef union uRFRFCTR {\r
+ CC_EXTENSION typedef union uRFRFCTR {\r
vuint16_t R;\r
struct {\r
vuint16_t:4;\r
vuint16_t F0EN:1; /* filter enable */\r
} B;\r
} RFRFCTR_t;\r
- typedef union uPCR0 {\r
+ CC_EXTENSION typedef union uPCR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR0_t;\r
\r
- typedef union uPCR1 {\r
+ CC_EXTENSION typedef union uPCR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} PCR1_t;\r
\r
- typedef union uPCR2 {\r
+ CC_EXTENSION typedef union uPCR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_AFTER_ACTION_POINT:6;\r
} B;\r
} PCR2_t;\r
\r
- typedef union uPCR3 {\r
+ CC_EXTENSION typedef union uPCR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_SYMBOL_RX_LOW:6;\r
} B;\r
} PCR3_t;\r
\r
- typedef union uPCR4 {\r
+ CC_EXTENSION typedef union uPCR4 {\r
vuint16_t R;\r
struct {\r
vuint16_t CAS_RX_LOW_MAX:7;\r
} B;\r
} PCR4_t;\r
\r
- typedef union uPCR5 {\r
+ CC_EXTENSION typedef union uPCR5 {\r
vuint16_t R;\r
struct {\r
vuint16_t TSS_TRANSMITTER:4;\r
} B;\r
} PCR5_t;\r
\r
- typedef union uPCR6 {\r
+ CC_EXTENSION typedef union uPCR6 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR6_t;\r
\r
- typedef union uPCR7 {\r
+ CC_EXTENSION typedef union uPCR7 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_B:9;\r
} B;\r
} PCR7_t;\r
\r
- typedef union uPCR8 {\r
+ CC_EXTENSION typedef union uPCR8 {\r
vuint16_t R;\r
struct {\r
vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;\r
} B;\r
} PCR8_t;\r
\r
- typedef union uPCR9 {\r
+ CC_EXTENSION typedef union uPCR9 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_EXISTS:1;\r
} B;\r
} PCR9_t;\r
\r
- typedef union uPCR10 {\r
+ CC_EXTENSION typedef union uPCR10 {\r
vuint16_t R;\r
struct {\r
vuint16_t SINGLE_SLOT_ENABLED:1;\r
} B;\r
} PCR10_t;\r
\r
- typedef union uPCR11 {\r
+ CC_EXTENSION typedef union uPCR11 {\r
vuint16_t R;\r
struct {\r
vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;\r
} B;\r
} PCR11_t;\r
\r
- typedef union uPCR12 {\r
+ CC_EXTENSION typedef union uPCR12 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;\r
} B;\r
} PCR12_t;\r
\r
- typedef union uPCR13 {\r
+ CC_EXTENSION typedef union uPCR13 {\r
vuint16_t R;\r
struct {\r
vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR13_t;\r
\r
- typedef union uPCR14 {\r
+ CC_EXTENSION typedef union uPCR14 {\r
vuint16_t R;\r
struct {\r
vuint16_t RATE_CORRECTION_OUT:11;\r
} B;\r
} PCR14_t;\r
\r
- typedef union uPCR15 {\r
+ CC_EXTENSION typedef union uPCR15 {\r
vuint16_t R;\r
struct {\r
vuint16_t LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR15_t;\r
\r
- typedef union uPCR16 {\r
+ CC_EXTENSION typedef union uPCR16 {\r
vuint16_t R;\r
struct {\r
vuint16_t MACRO_INITIAL_OFFSET_B:7;\r
} B;\r
} PCR16_t;\r
\r
- typedef union uPCR17 {\r
+ CC_EXTENSION typedef union uPCR17 {\r
vuint16_t R;\r
struct {\r
vuint16_t NOISE_LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR17_t;\r
\r
- typedef union uPCR18 {\r
+ CC_EXTENSION typedef union uPCR18 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_PATTERN:6;\r
} B;\r
} PCR18_t;\r
\r
- typedef union uPCR19 {\r
+ CC_EXTENSION typedef union uPCR19 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_A:9;\r
} B;\r
} PCR19_t;\r
\r
- typedef union uPCR20 {\r
+ CC_EXTENSION typedef union uPCR20 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_INITIAL_OFFSET_B:8;\r
} B;\r
} PCR20_t;\r
\r
- typedef union uPCR21 {\r
+ CC_EXTENSION typedef union uPCR21 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_RATE_CORRECTION:3;\r
} B;\r
} PCR21_t;\r
\r
- typedef union uPCR22 {\r
+ CC_EXTENSION typedef union uPCR22 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR22_t;\r
\r
- typedef union uPCR23 {\r
+ CC_EXTENSION typedef union uPCR23 {\r
vuint16_t R;\r
struct {\r
vuint16_t micro_per_cycle_l:16;\r
} B;\r
} PCR23_t;\r
\r
- typedef union uPCR24 {\r
+ CC_EXTENSION typedef union uPCR24 {\r
vuint16_t R;\r
struct {\r
vuint16_t CLUSTER_DRIFT_DAMPING:5;\r
} B;\r
} PCR24_t;\r
\r
- typedef union uPCR25 {\r
+ CC_EXTENSION typedef union uPCR25 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MIN_L:16;\r
} B;\r
} PCR25_t;\r
\r
- typedef union uPCR26 {\r
+ CC_EXTENSION typedef union uPCR26 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;\r
} B;\r
} PCR26_t;\r
\r
- typedef union uPCR27 {\r
+ CC_EXTENSION typedef union uPCR27 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MAX_L:16;\r
} B;\r
} PCR27_t;\r
\r
- typedef union uPCR28 {\r
+ CC_EXTENSION typedef union uPCR28 {\r
vuint16_t R;\r
struct {\r
vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;\r
} B;\r
} PCR28_t;\r
\r
- typedef union uPCR29 {\r
+ CC_EXTENSION typedef union uPCR29 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_OFFSET_CORRECTION:3;\r
} B;\r
} PCR29_t;\r
\r
- typedef union uPCR30 {\r
+ CC_EXTENSION typedef union uPCR30 {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} PCR30_t;\r
\r
- typedef struct uMSG_BUFF_CCS {\r
+ CC_EXTENSION typedef struct uMSG_BUFF_CCS {\r
union {\r
vuint16_t R;\r
struct {\r
volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */\r
} FR_tag_t;\r
\r
- typedef union uF_HEADER /* frame header */\r
+ CC_EXTENSION typedef union uF_HEADER /* frame header */\r
{\r
struct {\r
vuint16_t:5;\r
} B;\r
vuint16_t WORDS[3];\r
} F_HEADER_t;\r
- typedef union uS_STSTUS /* slot status */\r
+ CC_EXTENSION typedef union uS_STSTUS /* slot status */\r
{\r
struct {\r
vuint16_t VFB:1; /* Valid Frame on channel B */\r
\r
/* Define memories */\r
\r
+#if 0\r
#define SRAM_START 0x40000000\r
#define SRAM_SIZE 0x14000\r
#define SRAM_END 0x40013FFF\r
#define FLASH_START 0x0\r
#define FLASH_SIZE 0x200000\r
#define FLASH_END 0x1FFFFF\r
+#endif\r
\r
/* Define instances of modules */\r
#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)\r
projects / arc.git / blobdiff