* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-\r
-\r
+/*\r
+ * Freescale uses two flavors for DMA.\r
+ * 1. eDMA\r
+ * 2. eDMA + DMA_MUX\r
+ *\r
+ * 1. eDMA only (MPC5557, etc)\r
+ * The "DMA Request Assignments" are used and configured in Dma_Cfg.h using Dma_ChannelType.\r
+ *\r
+ * 2. eDMA + DMA_MUX (MPC551x , MPC5668, etc )\r
+ * The eDMA + DMA_MUX the "DMA Request Assignments" are just mappings from the DMA_MUX.\r
+ * The file Dma.h contains the Dma_MuxChannels\r
+ *\r
+ *\r
+ * eDMA+DMA_MUX\r
+ * MPC551x\r
+ * MPC5668\r
+ * MPC5605B,MPC5606B,MPC5607B\r
+ *\r
+ * eDMA\r
+ * MPC5567\r
+ *\r
+ * NO DMA\r
+ * MPC5604B\r
+ *\r
+ */\r
\r
#ifndef DMA_H_\r
#define DMA_H_\r
#include "Dma_Cfg.h"\r
#include "mpc55xx.h"\r
\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || (CFG_MPC5606S) || defined(CFG_MPC5668)\r
+#if !defined(CFG_DMA_MUX)\r
+#define CFG_DMA_MUX\r
+#endif\r
+#endif\r
+\r
+#if defined(CFG_DMA_MUX)\r
+\r
+#if defined(CFG_MPC5606S)\r
+typedef enum\r
+{\r
+ DMA_CHANNEL_DISABLED,\r
+\r
+ DMA_DSPI_0_TX,\r
+ DMA_DSPI_0_RX,\r
+ DMA_DSPI_1_TX,\r
+ DMA_DSPI_1_RX,\r
+\r
+ DMA_QuadSPI_0_TFFF,\r
+ DMA_QuadSPI_0_RFDF,\r
+\r
+ DMA_I2C_0_TX,\r
+ DMA_I2C_0_RX,\r
+ DMA_I2C_1_TX,\r
+ DMA_I2C_1_RX,\r
+ DMA_I2C_2_TX,\r
+ DMA_I2C_2_RX,\r
+ DMA_I2C_3_TX,\r
+ DMA_I2C_3_RX,\r
+\r
+ DMA_EMIOS200_0_FLAG_F0,\r
+ DMA_EMIOS200_0_FLAG_F1,\r
+ DMA_EMIOS200_0_FLAG_F2,\r
+ DMA_EMIOS200_0_FLAG_F3,\r
+ DMA_EMIOS200_0_FLAG_F4,\r
+ DMA_EMIOS200_0_FLAG_F5,\r
+ DMA_EMIOS200_0_FLAG_F6,\r
+ DMA_EMIOS200_0_FLAG_F7,\r
+ DMA_EMIOS200_0_FLAG_F8,\r
+ DMA_EMIOS200_0_FLAG_F9,\r
+ DMA_EMIOS200_0_FLAG_F10,\r
+ DMA_EMIOS200_0_FLAG_F11,\r
+ DMA_EMIOS200_0_FLAG_F12,\r
+ DMA_EMIOS200_0_FLAG_F13,\r
+ DMA_EMIOS200_0_FLAG_F14,\r
+ DMA_EMIOS200_0_FLAG_F15,\r
+ DMA_EMIOS200_1_FLAG_F0,\r
+ DMA_EMIOS200_1_FLAG_F1,\r
+ DMA_EMIOS200_1_FLAG_F2,\r
+ DMA_EMIOS200_1_FLAG_F3,\r
+ DMA_EMIOS200_1_FLAG_F4,\r
+ DMA_EMIOS200_1_FLAG_F5,\r
+ DMA_EMIOS200_1_FLAG_F6,\r
+ DMA_EMIOS200_1_FLAG_F7,\r
+\r
+ DMA_RESERVED1,\r
+ DMA_RESERVED2,\r
+ DMA_RESERVED3,\r
+ DMA_RESERVED4,\r
+ DMA_RESERVED5,\r
+ DMA_RESERVED6,\r
+ DMA_RESERVED7,\r
+ DMA_RESERVED8,\r
+\r
+ DMA_SIU_EISR_E1F1,\r
+ DMA_SIU_EISR_E1F2,\r
+ DMA_SIU_EISR_E1F3,\r
+ DMA_SIU_EISR_E1F4,\r
+\r
+ DMA_ADC,\r
+\r
+ DMA_RESERVED9,\r
+\r
+ DMA_DCU,\r
+\r
+ DMA_RESERVED10,\r
+ DMA_RESERVED11,\r
+\r
+ DMA_ALWAYS_REQUESTORS1,\r
+ DMA_ALWAYS_REQUESTORS2,\r
+ DMA_ALWAYS_REQUESTORS3,\r
+ DMA_ALWAYS_REQUESTORS4,\r
+ DMA_ALWAYS_REQUESTORS5,\r
+ DMA_ALWAYS_REQUESTORS6,\r
+ DMA_ALWAYS_REQUESTORS7,\r
+ DMA_ALWAYS_REQUESTORS8\r
+}Dma_MuxChannels;\r
+\r
+#elif defined(CFG_MPC5668)\r
+\r
+/* Table 22-4. DMA Source Configuration */\r
+\r
+typedef enum\r
+{\r
+ DMA_CHANNEL_DISABLED, /* 0 */\r
+ DMA_CHANNEL_RESERVED,\r
+ DMA_SCI_A_COMBTX,\r
+ DMA_SCI_A_COMBRX,\r
+ DMA_SCI_B_COMBTX,\r
+ DMA_SCI_B_COMBRX,\r
+ DMA_SCI_C_COMBTX,\r
+ DMA_SCI_C_COMBRX,\r
+ DMA_SCI_D_COMBTX,\r
+ DMA_SCI_D_COMBRX,\r
+ DMA_SCI_E_COMBTX,\r
+ DMA_SCI_E_COMBRX,\r
+ DMA_SCI_F_COMBTX,\r
+ DMA_SCI_F_COMBRX,\r
+ DMA_SCI_G_COMBTX,\r
+ DMA_SCI_G_COMBRX,\r
+ DMA_SCI_H_COMBTX,\r
+ DMA_SCI_H_COMBRX,\r
+\r
+ DMA_DSPI_A_SR_TFFF, /* 0x12 */\r
+ DMA_DSPI_A_SR_RFRD,\r
+ DMA_DSPI_B_SR_TFFF,\r
+ DMA_DSPI_B_SR_RFRD,\r
+ DMA_DSPI_E_SR_TFFF,\r
+ DMA_DSPI_E_SR_RFRD,\r
+ DMA_DSPI_F_SR_TFFF,\r
+ DMA_DSPI_F_SR_RFRD,\r
+\r
+ DMA_EMIOS200_FLAG_F0, /* 0x1a */\r
+ DMA_EMIOS200_FLAG_F1,\r
+ DMA_EMIOS200_FLAG_F2,\r
+ DMA_EMIOS200_FLAG_F3,\r
+ DMA_EMIOS200_FLAG_F4,\r
+ DMA_EMIOS200_FLAG_F5,\r
+ DMA_EMIOS200_FLAG_F6,\r
+ DMA_EMIOS200_FLAG_F7,\r
+ DMA_EMIOS200_FLAG_F8,\r
+ DMA_EMIOS200_FLAG_F9,\r
+ DMA_EMIOS200_FLAG_F10,\r
+ DMA_EMIOS200_FLAG_F11,\r
+ DMA_EMIOS200_FLAG_F12,\r
+ DMA_EMIOS200_FLAG_F13,\r
+ DMA_EMIOS200_FLAG_F14,\r
+ DMA_EMIOS200_FLAG_F15,\r
+\r
+ DMA_IIC_A_TX, /* 0x2a */\r
+ DMA_IIC_A_RX,\r
+ DMA_IIC_B_TX,\r
+ DMA_IIC_B_RX,\r
+\r
+ DMA_SIU_EISR_EIF0, /* 0x2e */\r
+ DMA_SIU_EISR_EIF1,\r
+\r
+ DMA_IIC_C_TX, /* 0x30 */\r
+ DMA_IIC_C_RX,\r
+\r
+ DMA_ADC_A,\r
+\r
+ DMA_IIC_D_TX, /* 0x33 */\r
+ DMA_IIC_D_RX,\r
+\r
+ DMA_SCI_J_COMBTX, /* 0x35 */\r
+ DMA_SCI_J_COMBRX,\r
+ DMA_SCI_K_COMBTX,\r
+ DMA_SCI_K_COMBRX,\r
+ DMA_SCI_L_COMBTX,\r
+ DMA_SCI_L_COMBRX,\r
+ DMA_SCI_M_COMBTX,\r
+ DMA_SCI_M_COMBRX,\r
+\r
+ DMA_ALWAYS_ENABLED_0, /* 0x3d */\r
+ DMA_ALWAYS_ENABLED_1,\r
+ DMA_ALWAYS_ENABLED_2,\r
+} Dma_MuxChannels;\r
+\r
+#elif defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+/* MPC551x "Table 13-4. DMA Source Configuration" */\r
+\r
typedef enum\r
{\r
DMA_CHANNEL_DISABLED,\r
DMA_ALWAYS_ENABLED8\r
}Dma_MuxChannels;\r
\r
+#endif\r
+#endif\r
+\r
+\r
+#if defined(CFG_DMA_MUX)\r
typedef struct\r
{\r
vuint8_t DMA_CHANNEL_ENABLE;\r
vuint8_t DMA_CHANNEL_TRIG_ENABLE;\r
Dma_MuxChannels DMA_CHANNEL_SOURCE;\r
} Dma_MuxConfigType;\r
+#endif\r
\r
typedef struct\r
{\r
typedef struct\r
{\r
// 5567 has no Dma Mux, but maybe this should be left in anyway?\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+#if defined(CFG_DMA_MUX)\r
const Dma_MuxConfigType *dmaMuxConfigPtr;\r
#endif\r
const Dma_ChannelConfigType *dmaChannelConfigPtr;\r
\r
\r
void Dma_Init (const Dma_ConfigType *ConfigPtr);\r
-void Dma_ConfigureChannel (struct tcd_t *tcd, Dma_ChannelType channel);\r
+void Dma_DeInit (void );\r
+void Dma_ConfigureChannel (Dma_TcdType *tcd, Dma_ChannelType channel);\r
void Dma_ConfigureChannelTranferSize (uint32_t nbrOfIterations, Dma_ChannelType channel);\r
void Dma_ConfigureChannelSourceCorr (uint32_t sourceCorrection, Dma_ChannelType channel);\r
void Dma_ConfigureChannelDestinationCorr (uint32_t destinationCorrection, Dma_ChannelType channel);\r
void Dma_StartChannel (Dma_ChannelType channel);\r
void Dma_StopChannel (Dma_ChannelType channel);\r
Std_ReturnType Dma_ChannelDone (Dma_ChannelType channel);\r
-volatile struct tcd_t * Dma_GetTcd( Dma_ChannelType channel );\r
+volatile Dma_TcdType * Dma_GetTcd( Dma_ChannelType channel );\r
boolean Dma_CheckConfig( void );\r
\r
#endif /* DMA_H_ */\r
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