* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-/* ----------------------------[includes]------------------------------------*/\r
#include <assert.h>\r
#include <string.h>\r
#include "Std_Types.h"\r
#include "Os.h"\r
#include "isr.h"\r
\r
-/* ----------------------------[private define]------------------------------*/\r
//#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
\r
-#define SYSCLOCK_SELECT_PLL 0x2\r
+#if defined(CFG_MPC5668) || defined(CFG_MPC5516)\r
+#define CFG_MCU_SUPPORT_SLEEP_MODE\r
+#endif\r
\r
-/* ----------------------------[private macro]-------------------------------*/\r
+\r
+#define SYSCLOCK_SELECT_PLL 0x2\r
\r
#if defined(CFG_MPC5567)\r
#define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \\r
( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )\r
-#elif defined(CFG_MPC5606S)\r
+#elif defined(CFG_MPC560X)\r
#define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \\r
( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )\r
#else\r
( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )\r
#endif\r
\r
-/* Development error macros. */\r
-#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
-#define VALIDATE(_exp,_api,_err ) \\r
- if( !(_exp) ) { \\r
- Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
- return; \\r
- }\r
-\r
-#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
- if( !(_exp) ) { \\r
- Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
- return (_rv); \\r
- }\r
-#else\r
-#define VALIDATE(_exp,_api,_err )\r
-#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
-#endif\r
+typedef void (*vfunc_t)();\r
\r
+/* Function declarations. */\r
+static void Mcu_ConfigureFlash(void);\r
\r
-/* ----------------------------[private typedef]-----------------------------*/\r
-typedef void (*vfunc_t)();\r
typedef struct{\r
uint32 lossOfLockCnt;\r
uint32 lossOfClockCnt;\r
Mcu_Stats stats;\r
} Mcu_GlobalType;\r
\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
\r
-/* ----------------------------[private function prototypes]-----------------*/\r
-static void Mcu_ConfigureFlash(void);\r
-/* ----------------------------[private variables]---------------------------*/\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
\r
// Global config\r
Mcu_GlobalType Mcu_Global =\r
.config = &McuConfigData[0],\r
};\r
\r
-/* ----------------------------[private functions]---------------------------*/\r
-/* ----------------------------[public functions]----------------------------*/\r
+//-------------------------------------------------------------------\r
\r
-/**\r
- * ISR wh\r
- */\r
-void Mcu_LossOfLock( void ) {\r
+void Mcu_LossOfLock( void ){\r
#if defined(USE_DEM)\r
Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);\r
#endif\r
* If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].\r
*\r
*/\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
/*not support*/\r
#else\r
Mcu_Global.stats.lossOfLockCnt++;\r
#endif\r
}\r
\r
-/**\r
- */\r
-static void Mcu_LossOfClock( void ){\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_LossOfClock( void ){\r
/* Should report MCU_E_CLOCK_FAILURE with DEM here */\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
/*not support*/\r
#else\r
Mcu_Global.stats.lossOfClockCnt++;\r
#define CORE_PVR_E200Z0 0x81710000UL\r
#define CORE_PVR_E200Z3 0x81120000UL\r
#define CORE_PVR_E200Z6 0x81170000UL\r
+#define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */\r
#define CORE_PVR_E200Z0H 0x817F0000UL\r
\r
typedef struct{\r
uint32 pvr;\r
} cpu_info_t;\r
\r
-cpu_info_t cpu_info_list[] = {\r
+const cpu_info_t cpu_info_list[] = {\r
#if defined(CFG_MPC5516)\r
{\r
.name = "MPC5516",\r
.name = "MPC563X",\r
.pvr = CORE_PVR_E200Z3,\r
},\r
+#elif defined(CFG_MPC5604B)\r
+ {\r
+ .name = "MPC5604B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5668)\r
+ {\r
+ .name = "MPC5668",\r
+ .pvr = CORE_PVR_E200Z65,\r
+ },\r
+ {\r
+ .name = "MPC5668",\r
+ .pvr = CORE_PVR_E200Z0,\r
+ },\r
#endif\r
};\r
\r
-core_info_t core_info_list[] = {\r
+const core_info_t core_info_list[] = {\r
#if defined(CFG_MPC5516)\r
{\r
.name = "CORE_E200Z1",\r
.name = "CORE_E200Z3",\r
.pvr = CORE_PVR_E200Z3,\r
},\r
+#elif defined(CFG_MPC5604B)\r
+ {\r
+ .name = "MPC5604B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
+#elif defined(CFG_MPC5606B)\r
+ {\r
+ .name = "MPC5606B",\r
+ .pvr = CORE_PVR_E200Z0H,\r
+ },\r
#elif defined(CFG_MPC5606S)\r
{\r
.name = "MPC5606S",\r
.pvr = CORE_PVR_E200Z0H,\r
},\r
+#elif defined(CFG_MPC5668)\r
+ {\r
+ .name = "CORE_E200Z65",\r
+ .pvr = CORE_PVR_E200Z65,\r
+ },\r
+ {\r
+ .name = "CORE_E200Z0",\r
+ .pvr = CORE_PVR_E200Z1,\r
+ },\r
#endif\r
};\r
\r
#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
#endif\r
\r
-static cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)\r
+static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)\r
{\r
int i;\r
\r
return NULL;\r
}\r
\r
-static core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
+static const core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
{\r
int i;\r
\r
\r
static uint32 Mcu_CheckCpu( void ) {\r
uint32 pvr;\r
- uint32 pir;\r
- cpu_info_t *cpuType;\r
- core_info_t *coreType;\r
+ // uint32 pir;\r
+ const cpu_info_t *cpuType;\r
+ const core_info_t *coreType;\r
\r
// We have to registers to read here, PIR and PVR\r
- pir = get_spr(SPR_PIR);\r
+ // pir = get_spr(SPR_PIR);\r
pvr = get_spr(SPR_PVR);\r
\r
cpuType = Mcu_IdentifyCpu(pvr);\r
return 0;\r
}\r
\r
-\r
//-------------------------------------------------------------------\r
\r
-void Mcu_Init(const Mcu_ConfigType *configPtr) {\r
-#if 0\r
- IRQ_DECL_ISR1( "LossOfLock", PLL_SYNSR_LOLF, CPU_CORE0, 10, Mcu_LossOfLock );\r
- IRQ_DECL_ISR1( "LossOfClock", PLL_SYNSR_LOCF, CPU_CORE0, 10, Mcu_LossOfClock );\r
-#endif\r
-\r
+void Mcu_Init(const Mcu_ConfigType *configPtr)\r
+{\r
VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
\r
+#if defined(CFG_MPC560X)\r
+ /* Disable watchdog. Watchdog is enabled default after reset.*/\r
+ SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */\r
+ SWT.SR.R = 0x0000d928;\r
+ SWT.CR.R = 0x8000010A; /* Disable watchdog */\r
+#if defined(USE_WDG)\r
+ SWT.TO.R = 0xfa00; /* set the timout to 500ms */\r
+ SWT.CR.R = 0x8000011B; /* enable watchdog */\r
+#endif\r
+#endif\r
+\r
if( !SIMULATOR() ) {\r
Mcu_CheckCpu();\r
}\r
\r
Mcu_Global.config = configPtr;\r
\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
/* Enable DRUN, RUN0, SAFE, RESET modes */\r
ME.MER.R = 0x0000001D;\r
#endif\r
Mcu_Global.initRun = 1;\r
\r
if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
/*not support*/\r
#else\r
ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );\r
-// Irq_AttachIsr1(Mcu_LossOfLock, NULL, PLL_SYNSR_LOLF,10 );\r
-// Irq_AttachIsr1(Mcu_LossOfLock, NULL, PLL_SYNSR_LOLF, 10);\r
-#if defined(CFG_MPC5516)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
FMPLL.ESYNCR2.B.LOLIRQ = 1;\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
FMPLL.SYNCR.B.LOLIRQ = 1;\r
#endif\r
ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );\r
-// Irq_AttachIsr1(Mcu_LossOfCLock, NULL, PLL_SYNSR_LOCF,10 );\r
-// IRQ_ATTACH( PLL_SYNSR_LOLF );\r
-// Irq_Attach( &IRQ_NAME(PLL_SYNSR_LOLF));\r
-// Irq_AttachIsr1(Mcu_LossOfClock, NULL, PLL_SYNSR_LOCF, 10);\r
-#if defined(CFG_MPC5516)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
FMPLL.ESYNCR2.B.LOCIRQ = 1;\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
FMPLL.SYNCR.B.LOCIRQ = 1;\r
\r
// TODO: find out if the 5554 really works like the 5516 here\r
// All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5554)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)\r
/* 5516clock info:\r
* Fsys - System frequency ( CPU + all periperals? )\r
*\r
assert(clockSettingsPtr->Pll2 < 16);\r
assert(clockSettingsPtr->Pll1 <= 4);\r
assert(clockSettingsPtr->Pll3 < 8);\r
-#else\r
-#error CPU not defined\r
#endif\r
\r
#if defined(USE_LDEBUG_PRINTF)\r
}\r
#endif\r
\r
-#if defined(CFG_MPC5516)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
+\r
+ // set post divider to next valid value to ensure that an overshoot during lock phase\r
+ // won't result in a too high freq\r
+ FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;\r
\r
// External crystal PLL mode.\r
FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?\r
// Write pll parameters.\r
FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;\r
FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;\r
- FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;\r
\r
+ while(FMPLL.SYNSR.B.LOCK != 1) {};\r
+\r
+ FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;\r
// Connect SYSCLK to FMPLL\r
SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;\r
+#elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)\r
+ // Write pll parameters.\r
+ CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;\r
+ CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;\r
+ CGM.FMPLL_CR.B.ODF = clockSettingsPtr->Pll3;\r
+\r
+ /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */\r
+ ME.RUN[0].R = 0x001F0074;\r
+ /* Peri. Cfg. 1 settings: only run in RUN0 mode */\r
+ ME.RUNPC[1].R = 0x00000010;\r
+ /* MPC56xxB/S: select ME.RUNPC[1] */\r
+ ME.PCTL[68].R = 0x01; //SIUL control\r
+ ME.PCTL[91].R = 0x01; //RTC/API control\r
+ ME.PCTL[92].R = 0x01; //PIT_RTI control\r
+ ME.PCTL[72].R = 0x01; //eMIOS0 control\r
+ ME.PCTL[73].R = 0x01; //eMIOS1 control\r
+ ME.PCTL[16].R = 0x01; //FlexCAN0 control\r
+ ME.PCTL[17].R = 0x01; //FlexCAN1 control\r
+ ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */\r
+ ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */\r
+ ME.PCTL[32].R = 0x01; //ADC0 control\r
+#if defined(CFG_MPC5606B)\r
+ ME.PCTL[33].R = 0x01; //ADC1 control\r
+#endif\r
+ ME.PCTL[23].R = 0x01; //DMAMUX control\r
+ ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
+ ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
+ /* Mode Transition to enter RUN0 mode: */\r
+ /* Enter RUN0 Mode & Key */\r
+ ME.MCTL.R = 0x40005AF0;\r
+ /* Enter RUN0 Mode & Inverted Key */\r
+ ME.MCTL.R = 0x4000A50F;\r
+\r
+ /* Wait for mode transition to complete */\r
+ while (ME.GS.B.S_MTRANS) {}\r
+ /* Verify RUN0 is the current mode */\r
+ while(ME.GS.B.S_CURRENTMODE != 4) {}\r
+\r
+ CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
+\r
+ SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */\r
+ SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */\r
+\r
#elif defined(CFG_MPC5606S)\r
// Write pll parameters.\r
CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;\r
ME.PCTL[73].R = 0x01; //eMIOS1 control\r
ME.PCTL[16].R = 0x01; //FlexCAN0 control\r
ME.PCTL[17].R = 0x01; //FlexCAN1 control\r
+ ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */\r
+ ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */\r
ME.PCTL[32].R = 0x01; //ADC0 control\r
-\r
+ ME.PCTL[23].R = 0x01; //DMAMUX control\r
+ ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
+ ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */\r
/* Mode Transition to enter RUN0 mode: */\r
/* Enter RUN0 Mode & Key */\r
ME.MCTL.R = 0x40005AF0;\r
/* Verify RUN0 is the current mode */\r
while(ME.GS.B.S_CURRENTMODE != 4) {}\r
\r
+ CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */\r
+ CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */\r
+ CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */\r
+\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
// Partially following the steps in MPC5567 RM..\r
FMPLL.SYNCR.B.DEPTH = 0;\r
while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;\r
\r
FMPLL.SYNCR.B.LOLIRQ = 1;\r
-#else\r
-#error CPU not defined\r
#endif\r
\r
return E_OK;\r
void Mcu_DistributePllClock(void)\r
{\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560XB)\r
+ VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
+#elif defined(CFG_MPC5606S)\r
VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
#else\r
VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );\r
\r
if( !SIMULATOR() )\r
{\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560XB)\r
+ if ( !CGM.FMPLL_CR.B.S_LOCK )\r
+ {\r
+ rv = MCU_PLL_UNLOCKED;\r
+ } else\r
+ {\r
+ rv = MCU_PLL_LOCKED;\r
+ }\r
+#elif defined(CFG_MPC5606S)\r
if ( !CGM.FMPLL[0].CR.B.S_LOCK )\r
{\r
rv = MCU_PLL_UNLOCKED;\r
\r
VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
if( RGM.FES.B.F_SOFT ) {\r
rv = MCU_SW_RESET;\r
} else if( RGM.DES.B.F_SWT ) {\r
return MCU_GETRESETRAWVALUE_UNINIT_RV;\r
}\r
\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
if( RGM.DES.R )\r
return RGM.DES.R;\r
else\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );\r
\r
// Reset\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
ME.MCTL.R = 0x00005AF0;\r
ME.MCTL.R = 0x0000A50F;\r
\r
\r
//-------------------------------------------------------------------\r
\r
-void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+/**\r
+ *\r
+ * Application Notes!\r
+ * - AN3584, "MPC5510 Family Low Power Features"\r
+ * Since it's not complete also check MPC5668\r
+ * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code\r
+ *\r
+ *\r
+ * @param LPM\r
+ */\r
+static void enterLowPower (Mcu_ModeType mcuMode )\r
{\r
+#if defined(CFG_MCU_SUPPORT_SLEEP_MODE)\r
+\r
+#if defined(CFG_MPC5668)\r
+ uint32 timeout;\r
+ /* Set the sleep bit; following a WAIT instruction, the device will go to sleep */\r
+ CRP.PSCR.B.SLEEP = 1;\r
+\r
+ /* 0x1 32k, 0x2 64k, 0x3 128k -- RAMs maintain power */\r
+ CRP.PSCR.B.RAMSEL = 0x3; // Keep all 128K\r
+\r
+ CRP.Z6VEC.R = (uint32)&McuE_LowPowerRecoverFlash;\r
+#if defined(CFG_VLE)\r
+ CRP.Z6VEC.VLE = 1;\r
+#endif\r
+\r
+ /* If we "Mcu_Wakeup()" is located in RAM, set FASTREC */\r
+ CRP.RECPTR.B.FASTREC = 0;\r
+\r
+ /* Halt everything */\r
+ SIU.HLT0.R = 0x037FFF3D;\r
+ SIU.HLT1.R = 0x18000F3C;\r
+ while((SIU.HLTACK0.R != 0x037FFF3D) && (SIU.HLTACK1.R != 0x18000F3C) && (timeout<3000)){}\r
+\r
+ /* put Z0 in reset if not used for wakeup */\r
+ CRP.Z0VEC.B.Z0RST = 1;\r
+\r
+ // TODO: Enable_all_internal_pull_devices (PULL_DOWN);\r
+\r
+ /* Save context and execute wait instruction.\r
+ *\r
+ * Things that matter here are\r
+ * - Z1VEC, determines where TLB0 will point. TLB0 is written with a\r
+ * value at startup that 4K aligned to this address.\r
+ * - LowPower_Sleep() will save a interrupt context so we will return\r
+ * intact.\r
+ * - For devices with little RAM we don't want to impose the alignment\r
+ * requirements there. Almost as we have to occupy a 4K block for this..\r
+ * although the code does not take that much space.\r
+ * */\r
+ McuE_EnterLowPower(mcuMode);\r
+\r
+ /* Clear sleep flags to allow pads to operate */\r
+ CRP.PSCR.B.SLEEPF = 0x1;\r
+\r
+#elif defined(CFG_MPC5516)\r
+ uint32 timeout;\r
+ /* Set the sleep bit; following a WAIT instruction, the device will go to sleep */\r
+ CRP.PSCR.B.SLEEP = 1;\r
+ /* enable the 1.2V internal regulator when in sleep mode only */\r
+ CRP.PSCR.B.STOP12EN = 1;\r
+ /* 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power */\r
+ CRP.PSCR.B.RAMSEL = 0x7; // Keep all 80K\r
+\r
+ CRP.Z1VEC.R = (uint32)&McuE_LowPowerRecoverFlash;\r
+#if defined(CFG_VLE)\r
+ CRP.VLE = 1;\r
+#endif\r
+\r
+ /* If we "Mcu_Wakeup()" is located in RAM, set FASTREC */\r
+ CRP.RECPRTR.B.FASTREC = 0;\r
+\r
+ /* Halt everything */\r
+ SIU.HLT.R = 0x3FFFFFFF;\r
+ while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout<3000)) {}\r
+\r
+ /* put Z0 in reset if not used for wakeup */\r
+ CRP.Z0VEC.B.Z0RST = 1;\r
+\r
+ // TODO: Enable_all_internal_pull_devices (PULL_DOWN);\r
+\r
+ /* Save context and execute wait instruction.\r
+ *\r
+ * Things that matter here are\r
+ * - Z1VEC, determines where TLB0 will point. TLB0 is written with a\r
+ * value at startup that 4K aligned to this address.\r
+ * - LowPower_Sleep() will save a interrupt context so we will return\r
+ * intact.\r
+ * - For devices with little RAM we don't want to impose the alignment\r
+ * requirements there. Almost as we have to occupy a 4K block for this..\r
+ * although the code does not take that much space.\r
+ * */\r
+ McuE_EnterLowPower(mcuMode);\r
+\r
+ /* Clear sleep flags to allow pads to operate */\r
+ CRP.PSCR.B.SLEEPF = 0x1;\r
+#else\r
+ /* NOT SUPPORTED */\r
+ (void) McuMode;\r
+#endif\r
+#endif\r
+}\r
+\r
+\r
+\r
+void Mcu_SetMode( Mcu_ModeType mcuMode)\r
+{\r
+\r
VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
// VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );\r
- (void) McuMode;\r
+#if defined(CFG_MCU_SUPPORT_SLEEP_MODE)\r
+\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
+ if( MCU_MODE_RUN == mcuMode ) {\r
+\r
+ } else if( MCU_MODE_SLEEP == mcuMode ) {\r
+ /*\r
+ * Follows the AN3548 from Freescale\r
+ *\r
+ */\r
+#if defined(USE_DMA)\r
+ Dma_StopAll();\r
+#endif\r
+\r
+\r
+ /* Set system clock to 16Mhz IRC */\r
+ SIU.SYSCLK.B.SYSCLKSEL = 0;\r
+\r
+ /* Put flash in low-power mode */\r
+ // TODO\r
+\r
+ /* Put QQADC in low-power mode */\r
+ // TODO\r
+\r
+ /* Set us in SLEEP mode */\r
+ CRP.PSCR.B.SLEEP = 1;\r
\r
+\r
+ enterLowPower(mcuMode);\r
+ }\r
+#else\r
/* NOT SUPPORTED */\r
+ (void) McuMode;\r
+#endif\r
+#endif\r
}\r
\r
//-------------------------------------------------------------------\r
* 563x - We run in legacy mode = 5567\r
* 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));\r
*/\r
-#if defined(CFG_MPC5516)\r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5668)\r
uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;\r
uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;\r
uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;\r
uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;\r
uint32_t emfd = FMPLL.SYNCR.B.MFD;\r
uint32_t erfd = FMPLL.SYNCR.B.RFD;\r
+#elif defined(CFG_MPC560XB)\r
+ uint32_t eprediv = CGM.FMPLL_CR.B.IDF;\r
+ uint32_t emfd = CGM.FMPLL_CR.B.NDIV;\r
+ uint32_t erfd = CGM.FMPLL_CR.B.ODF;\r
#elif defined(CFG_MPC5606S)\r
uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;\r
uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;\r
return f_sys;\r
}\r
\r
-imask_t McuE_EnterCriticalSection()\r
-{\r
- uint32_t msr = get_msr();\r
- Irq_Disable();\r
- return msr;\r
-}\r
+#if defined(CFG_MPC5668)\r
+uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {\r
+ uint32_t sysClock = McuE_GetSystemClock();\r
+ vuint32_t prescaler;\r
+\r
+ switch (type)\r
+ {\r
+ case PERIPHERAL_CLOCK_FLEXCAN_A:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_B:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_C:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_D:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_E:\r
+ case PERIPHERAL_CLOCK_FLEXCAN_F:\r
+ case PERIPHERAL_CLOCK_DSPI_A:\r
+ case PERIPHERAL_CLOCK_DSPI_B:\r
+ case PERIPHERAL_CLOCK_DSPI_C:\r
+ case PERIPHERAL_CLOCK_DSPI_D:\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV1;\r
+ break;\r
+ case PERIPHERAL_CLOCK_ESCI_A:\r
+ case PERIPHERAL_CLOCK_ESCI_B:\r
+ case PERIPHERAL_CLOCK_ESCI_C:\r
+ case PERIPHERAL_CLOCK_ESCI_D:\r
+ case PERIPHERAL_CLOCK_ESCI_E:\r
+ case PERIPHERAL_CLOCK_ESCI_F:\r
+ case PERIPHERAL_CLOCK_IIC_A:\r
+ case PERIPHERAL_CLOCK_IIC_B:\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV0;\r
+ break;\r
+ case PERIPHERAL_CLOCK_ADC_A:\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV2;\r
+ break;\r
+ case PERIPHERAL_CLOCK_EMIOS:\r
+ prescaler = SIU.SYSCLK.B.LPCLKDIV3;\r
+ break;\r
+ default:\r
+ assert(0);\r
+ break;\r
+ }\r
+\r
+ return sysClock/(1<<prescaler);\r
\r
-void McuE_ExitCriticalSection(uint32_t old_state)\r
-{\r
- set_msr(old_state);\r
}\r
\r
+#else\r
+\r
/**\r
* Get the peripheral clock in Hz for a specific device\r
- *\r
- * @param type\r
- * @return\r
*/\r
uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
{\r
#if defined(CFG_MPC5516)\r
prescaler = SIU.SYSCLK.B.LPCLKDIV0;\r
break;\r
-#elif defined(CFG_MPC5606S)\r
- prescaler = CGM.SC_DC[1].R;\r
+#elif defined(CFG_MPC560X)\r
+ prescaler = CGM.SC_DC[1].B.DIV;\r
break;\r
#endif\r
\r
#if defined(CFG_MPC5516)\r
prescaler = SIU.SYSCLK.B.LPCLKDIV2;\r
break;\r
-#elif defined(CFG_MPC5606S)\r
- prescaler = CGM.SC_DC[1].R;\r
+#elif defined(CFG_MPC560X)\r
+ prescaler = CGM.SC_DC[1].B.DIV;\r
break;\r
#endif\r
\r
case PERIPHERAL_CLOCK_DSPI_B:\r
case PERIPHERAL_CLOCK_DSPI_C:\r
case PERIPHERAL_CLOCK_DSPI_D:\r
+ case PERIPHERAL_CLOCK_DSPI_E:\r
+ case PERIPHERAL_CLOCK_DSPI_F:\r
#if defined(CFG_MPC5516)\r
prescaler = SIU.SYSCLK.B.LPCLKDIV3;\r
break;\r
break;\r
#endif\r
\r
-#if defined(CFG_MPC5606S)\r
+#if defined(CFG_MPC560X)\r
+ case PERIPHERAL_CLOCK_LIN_A:\r
+ case PERIPHERAL_CLOCK_LIN_B:\r
+#if defined(CFG_MPC560XB)\r
+ case PERIPHERAL_CLOCK_LIN_C:\r
+ case PERIPHERAL_CLOCK_LIN_D:\r
+#endif\r
+ prescaler = CGM.SC_DC[0].B.DIV;\r
+ break;\r
case PERIPHERAL_CLOCK_EMIOS_0:\r
- prescaler = CGM.SC_DC[2].R;\r
+ prescaler = CGM.SC_DC[2].B.DIV;\r
break;\r
case PERIPHERAL_CLOCK_EMIOS_1:\r
- prescaler = CGM.SC_DC[2].R;\r
+ prescaler = CGM.SC_DC[2].B.DIV;\r
break;\r
#else\r
case PERIPHERAL_CLOCK_EMIOS:\r
return sysClock/(1<<prescaler);\r
#endif\r
}\r
-\r
+#endif\r
\r
/**\r
* Function to setup the internal flash for optimal performance\r
\r
/* Enable pipelined reads again. */\r
FLASH.MCR.B.PRD = 0;\r
+#elif defined(CFG_MPC5668)\r
+ /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */\r
+\r
+ /* Should probably trim this values */\r
+ const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,\r
+ .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,\r
+ .BFEN = 1 };\r
+ FLASH.PFCRP0.B = val;\r
+\r
+ /* Enable pipelined reads again. */\r
#elif defined(CFG_MPC5554) || defined(CFG_MPC5567)\r
//TODO: Lägg till flash för mpc5554 &67\r
#endif\r
}\r
\r
-void McuE_EnableInterrupts(void)\r
-{\r
- Irq_Enable();\r
-}\r
-\r
-void McuE_DisableInterrupts(void)\r
-{\r
- Irq_Disable();\r
-}\r
projects / arc.git / blobdiff