-/*\r
- * core_cr4.h\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
*\r
- * Created on: 12 okt 2010\r
- * Author: maek\r
- */\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
\r
#ifndef CORE_CR4_H_\r
#define CORE_CR4_H_\r
\r
+#include "Std_Types.h"\r
+\r
#define __I volatile const /*!< defines 'read only' permissions */\r
#define __O volatile /*!< defines 'write only' permissions */\r
#define __IO volatile /*!< defines 'read / write' permissions */\r
#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
\r
\r
+/*----------------------------------------------------------------------------*/\r
+/* CAN register definition */\r
+\r
+typedef volatile struct\r
+{\r
+ uint32 CTL;\r
+ uint32 SR;\r
+ unsigned : 16; /* bits 31-16 - Reserved; 0x0008 - Error Counter Register */\r
+ unsigned REC : 8; /* bits 15-8 - Receive Error Counter; 0x0008 - Error Counter Register */\r
+ unsigned TEC : 8; /* bits 7-0 - Transmit Error Counter; 0x0008 - Error Counter Register */\r
+ uint32 BTR;\r
+ uint32 IR;\r
+ uint32 TR;\r
+ unsigned : 32;\r
+ uint32 PEC;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 ABOT;\r
+ uint32 TRX;\r
+ uint32 TRx[4];\r
+ uint32 NDX;\r
+ uint32 NDx[4];\r
+ uint32 IPX;\r
+ uint32 IPx[4];\r
+ uint32 MVX;\r
+ uint32 MVx[4];\r
+ unsigned : 32;\r
+ uint32 IPMx[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ struct\r
+ {\r
+ uint32 COM; /* 0x0100: IF1 Command Register - Reserved, Command, Status, Msg Number */\r
+ uint32 MASK;\r
+ uint32 ARB;\r
+ uint32 MC;\r
+ uint8 DATx[8];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ } IFx[3];\r
+ uint32 IF3UEy[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 IOTX;\r
+ uint32 IORX;\r
+} Can_RegisterType;\r
+\r
+\r
+#define DCAN1_Base ((Can_RegisterType *)0xFFF7DC00)\r
+#define DCAN2_Base ((Can_RegisterType *)0xFFF7DE00)\r
+#define DCAN3_Base ((Can_RegisterType *)0xFFF7E000)\r
+\r
+\r
+\r
+typedef volatile struct gioBase\r
+{\r
+ unsigned GCR0; /**< 0x0000: Global Control Register */\r
+ unsigned PWDN; /**< 0x0004: Power Down Register */\r
+ unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/\r
+ unsigned POL; /**< 0x000C: Interrupt Polarity Register */\r
+ unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */\r
+ unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */\r
+ unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */\r
+ unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */\r
+ unsigned FLG; /**< 0x0020: Interrupt Flag Register */\r
+ unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
+ unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
+} GIO_Base_RegisterType;\r
+\r
+\r
+/** @struct gioPort\r
+* @brief GIO Port Register Definition\r
+*/\r
+/** @typedef gioPORT_t\r
+* @brief GIO Port Register Type Definition\r
+*\r
+* This type is used to access the GIO Port Registers.\r
+*/\r
+typedef volatile struct gioPort\r
+{\r
+ unsigned DIR; /**< 0x0000: Data Direction Register */\r
+ unsigned DIN; /**< 0x0004: Data Input Register */\r
+ unsigned DOUT; /**< 0x0008: Data Output Register */\r
+ unsigned DSET; /**< 0x000C: Data Output Set Register */\r
+ unsigned DCLR; /**< 0x0010: Data Output Clear Register */\r
+ unsigned PDR; /**< 0x0014: Open Drain Regsiter */\r
+ unsigned PULDIS; /**< 0x0018: Pullup Disable Register */\r
+ unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
+} GIO_RegisterType;\r
+\r
+/** @def GIO_PORTA_BASE\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)\r
+/** @def GIO_PORTB_BASE\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)\r
+#define GIO_HET_PORT1_BASE ((GIO_RegisterType *)0xFFF7B84CU)\r
+\r
+/** @def gioREG\r
+* @brief GIO Register Frame Pointer\r
+*\r
+* This pointer is used by the GIO driver to access the gio module registers.\r
+*/\r
+#define gioREG ((GIO_Base_RegisterType *)0xFFF7BC00U)\r
+\r
+\r
+/** @struct dmmBase\r
+* @brief DMM Base Register Definition\r
+*\r
+* This structure is used to access the DMM module egisters.\r
+*/\r
+/** @typedef dmmBASE_t\r
+* @brief DMM Register Frame Type Definition\r
+*\r
+* This type is used to access the DMM Registers.\r
+*/\r
+\r
+typedef volatile struct dmmBase\r
+{\r
+ unsigned GLBCTRL; /**< 0x0000: Global control register 0 */\r
+ unsigned INTSET; /**< 0x0004: DMM Interrupt Set Register */\r
+ unsigned INTCLR; /**< 0x0008: DMM Interrupt Clear Register */\r
+ unsigned INTLVL; /**< 0x000C: DMM Interrupt Level Register */\r
+ unsigned INTFLG; /**< 0x0010: DMM Interrupt Flag Register */\r
+ unsigned OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */\r
+ unsigned OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */\r
+ unsigned DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */\r
+ unsigned DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */\r
+ unsigned DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */\r
+ unsigned INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */\r
+ unsigned DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */\r
+ unsigned DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */\r
+ unsigned DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */\r
+ unsigned DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */\r
+ unsigned DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */\r
+ unsigned DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */\r
+ unsigned DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */\r
+ unsigned DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */\r
+ unsigned DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */\r
+ unsigned DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */\r
+ unsigned DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */\r
+ unsigned DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */\r
+ unsigned DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */\r
+ unsigned DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */\r
+ unsigned DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */\r
+ unsigned DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */\r
+ unsigned PC0; /**< 0x006C: DMM Pin Control 0 */\r
+ unsigned PC1; /**< 0x0070: DMM Pin Control 1 */\r
+ unsigned PC2; /**< 0x0074: DMM Pin Control 2 */\r
+ unsigned PC3; /**< 0x0078: DMM Pin Control 3 */\r
+ unsigned PC4; /**< 0x007C: DMM Pin Control 4 */\r
+ unsigned PC5; /**< 0x0080: DMM Pin Control 5 */\r
+ unsigned PC6; /**< 0x0084: DMM Pin Control 6 */\r
+ unsigned PC7; /**< 0x0088: DMM Pin Control 7 */\r
+ unsigned PC8; /**< 0x008C: DMM Pin Control 8 */\r
+} DMM_Base_RegisterType;\r
+\r
+#define dmmReg ((DMM_Base_RegisterType *)0xFFFFF700U)\r
+\r
+#define GIO_DMM_PORT_BASE ((GIO_RegisterType *)0xFFFFF770U)\r
+\r
typedef struct\r
{\r
__IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
__I uint32_t CALIB; /*!< SysTick Calibration Register */\r
} SysTick_Type;\r
\r
+\r
static inline void __disable_irq() {\r
__asm volatile("CPSID if");\r
}\r
static inline void __enable_irq() {\r
__asm volatile("CPSIE if");\r
-\r
- /*\r
- __asm volatile("MRS R1, CPSR");\r
- __asm volatile("BIC R1, R1, #0x80");\r
- __asm volatile("MSR CPSR, R1");\r
-\r
- __asm volatile("MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0");\r
- __asm volatile("ORR R1 ,R1 ,#0x01000000"); //Mask 0-31 bits except bit 24 in Sys ; Ctrl Reg of CORTEX-R4\r
- __asm volatile("MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0"); //; Enable bit 24\r
- //__asm volatile("SVC #1");\r
- */\r
-\r
}\r
\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ register unsigned long val asm("r0");\r
+ asm("mrs r0, cpsr");\r
+ asm("and r0, r0, #0xC0"); // Mask the I and F bit of CPSR\r
+ __disable_irq();\r
+ return val;\r
+}\r
\r
-\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ if (mask & 0x80) {\r
+ __asm volatile("CPSID i");\r
+ } else {\r
+ __asm volatile("CPSIE i");\r
+ }\r
+ if (mask & 0x40) {\r
+ __asm volatile("CPSID f");\r
+ } else {\r
+ __asm volatile("CPSIE f");\r
+ }\r
+}\r
\r
#endif /* CORE_CR4_H_ */\r
projects / arc.git / blobdiff