1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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19 #ifndef USE_CAN_STUB
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20 #include "mpc55xx.h"
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23 #include "CanIf_Cbk.h"
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25 #if defined(USE_DEM)
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31 #if defined(USE_KERNEL)
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38 /* CONFIGURATION NOTES
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39 * ------------------------------------------------------------------
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40 * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC
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41 * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported
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42 * i.e CanIdValue is NOT supported
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43 * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT
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44 * ie CAN_ARC_PROCESS_TYPE_POLLED not supported
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45 * - To select the Mailboxes to use in the CAN controller use Can_Arc_MbMask
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46 * - HOH's for Tx are global and Rx are for each controller
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47 * - CanControllerTimeQuanta is NOT used. The other CanControllerXXX selects
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48 * the proper time-quanta
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49 * - Can_Arc_MbMask for Tx HOH must NOT overlap Can_Arc_MbMask for Rx.
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50 * - ONLY global mask is supported( NOT 14,15 and individual )
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51 * - Numbering the CanObjectId for Tx:
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52 * To do this correctly there are a number of things that are good to know
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53 * 1. HTH's have unique numbers.
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54 * 2. One HTH/HRH is maped to one HOH
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55 * 3. The extension Can_Arc_MbMask binds FULL CAN boxes together.
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60 * ---------------------
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65 * 17 | The use of Can_Arc_MbMask=0x000f0000 binds these to HTH 16
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66 * 18 | ( bits 16 to 19 set here )
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74 * C - Controller number
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78 /* IMPLEMENTATION NOTES
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79 * -----------------------------------------------
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80 * - A HOH us unique for a controller( not a config-set )
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81 * - Hrh's are numbered for each controller from 0
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82 * - HOH is numbered for each controller in sequences of 0-31
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83 * ( since we have 6 controllers and Hth is only uint8( See Can_Write() proto )
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84 * - loopback in HW NOT supported
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85 * - 32 of 64 boxes supported ( limited by Hth type )
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86 * - Fifo in HW NOT supported
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90 * -----------------------------------------------
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91 * - Can Hardware unit - One or multiple Can controllers of the same type.
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92 * - Hrh - HOH with receive definitions
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93 * - Hth - HOH with transmit definitions
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98 * ------------------------------------------------------------------
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99 * This controller should really be called FlexCan+ or something because
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100 * it's enhanced with:
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101 * - A RX Fifo !!!!! ( yep, it's fantastic ;) )
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102 * - A better matching process. From 25.4.4
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103 * "By programming more than one MB with the same ID, received messages will
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104 * be queued into the MBs. The CPU can examine the time stamp field of the
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105 * MBs to determine the order in which the messages arrived."
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107 * Soo, now it seems that Freescale have finally done something right.
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110 //-------------------------------------------------------------------
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112 // Number of mailboxes used for each controller ( power of 2 only )
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113 // ( It's NOT supported to set this to 64 )
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114 #define MAX_NUM_OF_MAILBOXES 32
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116 #if defined(CFG_MPC5567)
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117 #define GET_CONTROLLER(_controller) \
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118 ((struct FLEXCAN2_tag *)(0xFFFC0000 + 0x4000*(_controller)))
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120 #define GET_CONTROLLER(_controller) \
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121 ((struct FLEXCAN_tag *)(0xFFFC0000 + 0x4000*(_controller)))
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124 #define GET_CONTROLLER_CONFIG(_controller) \
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125 &Can_Global.config->CanConfigSet->CanController[(_controller)]
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127 #define GET_CALLBACKS() \
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128 (Can_Global.config->CanConfigSet->CanCallbacks)
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130 #define GET_PRIVATE_DATA(_controller) \
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131 &CanUnit[_controller]
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133 #define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)
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136 #define _INSTALL_HANDLER(_can_entry, _unique, _vector,_priority,_app ) \
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138 const OsIsrConstType _can_entry ## _unique = { \
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139 .vector = _vector, \
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140 .type = ISR_TYPE_2, \
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141 .priority = _priority, \
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142 .entry = _can_entry, \
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144 .resourceMask = 0, \
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145 .timingProtPtr = NULL, \
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146 .appOwner = _app, \
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148 Os_IsrAdd( & _can_entry ## _unique); \
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152 #define INSTALL_HANDLER4(_name,_can_entry, _vector,_priority,_app)\
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153 ISR_INSTALL_ISR2(_name,_can_entry, _vector+0,_priority,_app) \
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154 ISR_INSTALL_ISR2(_name,_can_entry, _vector+1,_priority,_app) \
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155 ISR_INSTALL_ISR2(_name,_can_entry, _vector+2,_priority,_app) \
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156 ISR_INSTALL_ISR2(_name,_can_entry, _vector+3,_priority,_app)
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158 #define INSTALL_HANDLER16(_name,_can_entry, _vector,_priority,_app)\
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159 INSTALL_HANDLER4(_name,_can_entry, _vector+0,_priority,_app) \
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160 INSTALL_HANDLER4(_name,_can_entry, _vector+4,_priority,_app) \
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161 INSTALL_HANDLER4(_name,_can_entry, _vector+8,_priority,_app) \
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162 INSTALL_HANDLER4(_name,_can_entry, _vector+12,_priority,_app)
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165 //-------------------------------------------------------------------
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167 #if ( CAN_DEV_ERROR_DETECT == STD_ON )
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168 #define VALIDATE(_exp,_api,_err ) \
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170 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
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171 return CAN_NOT_OK; \
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174 #define VALIDATE_NO_RV(_exp,_api,_err ) \
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176 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
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180 #define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)
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182 #define VALIDATE(_exp,_api,_err )
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183 #define VALIDATE_NO_RV(_exp,_api,_err )
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184 #define DET_REPORTERROR(_x,_y,_z,_q)
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187 #if defined(USE_DEM)
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188 #define VALIDATE_DEM_NO_RV(_exp,_err ) \
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190 Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
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194 #define VALIDATE_DEM_NO_RV(_exp,_err )
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197 //-------------------------------------------------------------------
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199 // Message box status defines
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200 #define MB_TX_ONCE 0xc
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201 #define MB_INACTIVE 0x8
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203 #define MB_ABORT 0x9
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205 //-------------------------------------------------------------------
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210 } Can_DriverStateType;
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216 vuint32_t TWRNINT:1;
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217 vuint32_t RWRNINT:1;
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218 vuint32_t BIT1ERR:1;
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219 vuint32_t BIT0ERR:1;
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220 vuint32_t ACKERR:1;
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221 vuint32_t CRCERR:1;
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222 vuint32_t FRMERR:1;
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223 vuint32_t STFERR:1;
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228 vuint32_t FLTCONF:2;
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230 vuint32_t BOFFINT:1;
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231 vuint32_t ERRINT:1;
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232 vuint32_t WAKINT:1;
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234 } ESRType; /* Error and Status Register */
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236 #if defined(CFG_MPC5567)
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237 typedef struct FLEXCAN2_tag flexcan_t;
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239 typedef struct FLEXCAN_tag flexcan_t;
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242 // Mapping between HRH and Controller//HOH
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243 typedef struct Can_Arc_ObjectHOHMapStruct
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245 uint32 HxHRef; // Reference to HRH or HTH
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246 CanControllerIdType CanControllerRef; // Reference to controller
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247 const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.
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248 } Can_Arc_ObjectHOHMapType;
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250 /* Type for holding global information used by the driver */
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252 Can_DriverStateType initRun;
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255 const Can_ConfigType *config;
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257 // One bit for each channel that is configured.
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258 // Used to determine if validity of a channel
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260 // 0 - NOT configured
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262 // Maps the a channel id to a configured channel id
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263 uint8 channelMap[CAN_CONTROLLER_CNT];
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265 // This is a map that maps the HTH:s with the controller and Hoh. It is built
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266 // during Can_Init and is used to make things faster during a transmit.
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267 Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];
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271 Can_GlobalType Can_Global =
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273 .initRun = CAN_UNINIT,
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277 /* Type for holding information about each controller */
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279 CanIf_ControllerModeType state;
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281 // Interrupt masks that is for all Mb's in this controller
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282 uint32 Can_Arc_RxMbMask;
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283 uint32 Can_Arc_TxMbMask;
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285 // Used at IFLG in controller at startup
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289 Can_Arc_StatisticsType stats;
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291 // Data stored for Txconfirmation callbacks to CanIf
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292 PduIdType swPduHandles[MAX_NUM_OF_MAILBOXES];
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296 Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =
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299 .state = CANIF_CS_UNINIT,
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301 .state = CANIF_CS_UNINIT,
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303 .state = CANIF_CS_UNINIT,
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305 .state = CANIF_CS_UNINIT,
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307 .state = CANIF_CS_UNINIT,
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309 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
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311 .state = CANIF_CS_UNINIT,
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316 //-------------------------------------------------------------------
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318 //-------------------------------------------------------------------
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320 * Function that finds the Hoh( HardwareObjectHandle ) from a Hth
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321 * A HTH may connect to one or several HOH's. Just find the first one.
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323 * @param hth The transmit handle
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324 * @returns Ptr to the Hoh
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326 static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)
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328 const Can_HardwareObjectType *hohObj;
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329 const Can_Arc_ObjectHOHMapType *map;
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330 const Can_ControllerConfigType *canHwConfig;
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332 map = &Can_Global.CanHTHMap[hth];
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334 // Verify that this is the correct map
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335 if (map->HxHRef != hth)
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337 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
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340 canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);
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342 hohObj = map->CanHOHRef;
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344 // Verify that this is the correct Hoh type
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345 if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
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347 *controller = map->CanControllerRef;
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351 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
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356 //-------------------------------------------------------------------
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358 static void Can_Isr( int unit );
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359 static void Can_Err( int unit );
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360 static void Can_BusOff( int unit );
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362 void Can_A_Isr( void ) { Can_Isr(CAN_CTRL_A); }
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363 void Can_B_Isr( void ) { Can_Isr(CAN_CTRL_B); }
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364 void Can_C_Isr( void ) { Can_Isr(CAN_CTRL_C); }
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365 void Can_D_Isr( void ) { Can_Isr(CAN_CTRL_D); }
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366 void Can_E_Isr( void ) { Can_Isr(CAN_CTRL_E); }
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367 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
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368 void Can_F_Isr( void ) { Can_Isr(CAN_CTRL_F); }
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371 void Can_A_Err( void ) { Can_Err(CAN_CTRL_A); }
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372 void Can_B_Err( void ) { Can_Err(CAN_CTRL_B); }
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373 void Can_C_Err( void ) { Can_Err(CAN_CTRL_C); }
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374 void Can_D_Err( void ) { Can_Err(CAN_CTRL_D); }
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375 void Can_E_Err( void ) { Can_Err(CAN_CTRL_E); }
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376 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
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377 void Can_F_Err( void ) { Can_Err(CAN_CTRL_F); }
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380 void Can_A_BusOff( void ) { Can_BusOff(CAN_CTRL_A); }
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381 void Can_B_BusOff( void ) { Can_BusOff(CAN_CTRL_B); }
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382 void Can_C_BusOff( void ) { Can_BusOff(CAN_CTRL_C); }
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383 void Can_D_BusOff( void ) { Can_BusOff(CAN_CTRL_D); }
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384 void Can_E_BusOff( void ) { Can_BusOff(CAN_CTRL_E); }
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385 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
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386 void Can_F_BusOff( void ) { Can_BusOff(CAN_CTRL_F); }
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388 //-------------------------------------------------------------------
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392 * Hardware error ISR for CAN
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394 * @param unit CAN controller number( from 0 )
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397 static void Can_Err( int unit ) {
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398 flexcan_t *canHw = GET_CONTROLLER(unit);
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399 Can_Arc_ErrorType err;
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403 esr.R = canHw->ESR.R;
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405 err.B.ACKERR = esr.B.ACKERR;
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406 err.B.BIT0ERR = esr.B.BIT0ERR;
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407 err.B.BIT1ERR = esr.B.BIT1ERR;
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408 err.B.CRCERR = esr.B.CRCERR;
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409 err.B.FRMERR = esr.B.FRMERR;
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410 err.B.STFERR = esr.B.STFERR;
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411 err.B.RXWRN = esr.B.RXWRN;
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412 err.B.TXWRN = esr.B.TXWRN;
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414 if (GET_CALLBACKS()->Arc_Error != NULL)
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416 GET_CALLBACKS()->Arc_Error(unit, err );
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419 canHw->ESR.B.ERRINT = 1;
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423 // Uses 25.4.5.1 Transmission Abort Mechanism
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424 static void Can_AbortTx( flexcan_t *canHw, Can_UnitType *canUnit ) {
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428 // Find our Tx boxes.
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429 mbMask = canUnit->Can_Arc_TxMbMask;
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431 // Loop over the Mb's set to abort
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432 for (; mbMask; mbMask&=~(1<<mbNr)) {
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433 mbNr = ilog2(mbMask);
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435 canHw->BUF[mbNr].CS.B.CODE = MB_ABORT;
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438 if( canHw->BUF[mbNr].CS.B.CODE != MB_ABORT ) {
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441 // it's not sent... or being sent.
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442 // Just wait for it
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444 while( canHw->IFRL.R == (1<<mbNr) )
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453 // Ack tx interrupts
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454 canHw->IFRL.R = canUnit->Can_Arc_TxMbMask;
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455 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
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458 //-------------------------------------------------------------------
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461 * BussOff ISR for CAN
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463 * @param unit CAN controller number( from 0 )
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465 static void Can_BusOff( int unit ) {
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466 flexcan_t *canHw = GET_CONTROLLER(unit);
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467 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
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468 Can_Arc_ErrorType err;
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471 if ( canHw->ESR.B.TWRNINT )
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473 err.B.TXWRN = canHw->ESR.B.TXWRN;
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474 canUnit->stats.txErrorCnt++;
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475 canHw->ESR.B.TWRNINT = 1;
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478 if ( canHw->ESR.B.RWRNINT )
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480 err.B.RXWRN = canHw->ESR.B.RXWRN;
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481 canUnit->stats.rxErrorCnt++;
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482 canHw->ESR.B.RWRNINT = 1;
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487 if (GET_CALLBACKS()->Arc_Error != NULL)
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489 GET_CALLBACKS()->Arc_Error( unit, err );
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493 if( canHw->ESR.B.BOFFINT ) {
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495 canUnit->stats.boffCnt++;
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496 if (GET_CALLBACKS()->ControllerBusOff != NULL)
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498 GET_CALLBACKS()->ControllerBusOff(unit);
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500 Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272
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502 canHw->ESR.B.BOFFINT = 1;
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504 Can_AbortTx( canHw, canUnit ); // CANIF273
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508 //-------------------------------------------------------------------
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511 * ISR for CAN. Normal Rx/Tx operation
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513 * @param unit CAN controller number( from 0 )
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515 static void Can_Isr(int unit) {
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517 flexcan_t *canHw= GET_CONTROLLER(unit);
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518 const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);
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519 uint32 iFlagLow = canHw->IFRL.R;
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520 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
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522 // Read interrupt flags to seeTxConfirmation what interrupt triggered the interrupt
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523 if (iFlagLow & canHw->IMRL.R) {
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526 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
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528 // FIFO code NOT tested
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529 if (canHw->MCR.B.FEN) {
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532 if (iFlagLow & (1<<7)) {
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533 canUnit->stats.fifoOverflow++;
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534 canHw->IFRL.B.BUF07I = 1;
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538 if (iFlagLow & (1<<6)) {
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539 canUnit->stats.fifoWarning++;
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540 canHw->IFRL.B.BUF06I = 1;
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543 // Pop fifo "realtime"
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544 while (canHw->IFRL.B.BUF05I) {
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546 // TODO MAHI: Must read the entire data-buffer to unlock??
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547 if (GET_CALLBACKS()->RxIndication != NULL)
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549 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
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550 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
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552 // Clear the interrupt
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553 canHw->IFRL.B.BUF05I = 1;
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558 const Can_HardwareObjectType *hohObj;
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565 // Loop over all the Hoh's
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569 hohObj= canHwConfig->Can_Arc_Hoh;
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574 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
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576 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
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578 // Loop over the Mb's for this Hoh
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579 for (; mbMask; mbMask&=~(1<<mbNr)) {
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580 mbNr = ilog2(mbMask);
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582 // Do the necessary dummy reads to keep controller happy
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583 data = canHw->BUF[mbNr].CS.R;
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584 data = canHw->BUF[mbNr].DATA.W[0];
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586 // According to autosar MSB shuould be set if extended
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587 if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {
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588 id = canHw->BUF[mbNr].ID.R;
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591 id = canHw->BUF[mbNr].ID.B.STD_ID;
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594 if (GET_CALLBACKS()->RxIndication != NULL)
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596 GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,
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598 canHw->BUF[mbNr].CS.B.LENGTH,
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599 (uint8 *)&canHw->BUF[mbNr].DATA.W[0] );
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601 // Increment statistics
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602 canUnit->stats.rxSuccessCnt++;
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604 // unlock MB (dummy read timer)
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608 canHw->IFRL.R = (1<<mbNr);
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611 } while ( !hohObj->Can_Arc_EOL);
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614 hohObj= canHwConfig->Can_Arc_Hoh;
\r
619 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
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621 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
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623 // Loop over the Mb's for this Hoh
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624 for (; mbMask; mbMask&=~(1<<mbNr)) {
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625 mbNr = ilog2(mbMask);
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627 if (GET_CALLBACKS()->TxConfirmation != NULL)
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629 GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandles[mbNr]);
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631 canUnit->swPduHandles[mbNr] = 0; // Is this really necessary ??
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634 canUnit->iflagStart |= (1<<mbNr);
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635 canHw->IFRL.R = (1<<mbNr);
\r
638 } while ( !hohObj->Can_Arc_EOL);
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639 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
643 // Note! Over 32 boxes is not implemented
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644 // Other reasons that we end up here
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645 // - Interupt on a masked box
\r
648 if (canHwConfig->Can_Arc_Fifo) {
\r
651 * Do not enable RxFIFO. See [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 14593].
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655 * NOT tested at all
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657 while (canHw->IFRL.B.BUF05I) {
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659 // TODO MAHI: Must read the entire data-buffer to unlock??
\r
660 if (GET_CALLBACKS()->RxIndication != NULL)
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662 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
\r
663 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
\r
665 // Increment statistics
\r
666 canUnit->stats.rxSuccessCnt++;
\r
668 // Clear the interrupt
\r
669 canHw->IFRL.B.BUF05I = 1;
\r
675 //-------------------------------------------------------------------
\r
678 // This initiates ALL can controllers
\r
679 void Can_Init( const Can_ConfigType *config ) {
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680 Can_UnitType *canUnit;
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681 const Can_ControllerConfigType *canHwConfig;
\r
685 VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );
\r
686 VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );
\r
689 Can_Global.config = config;
\r
690 Can_Global.initRun = CAN_READY;
\r
693 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
694 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
695 ctlrId = canHwConfig->CanControllerId;
\r
697 // Assign the configuration channel used later..
\r
698 Can_Global.channelMap[canHwConfig->CanControllerId] = configId;
\r
699 Can_Global.configured |= (1<<ctlrId);
\r
701 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
702 canUnit->state = CANIF_CS_STOPPED;
\r
704 canUnit->lock_cnt = 0;
\r
707 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
709 Can_InitController(ctlrId, canHwConfig);
\r
711 // Loop through all Hoh:s and map them into the HTHMap
\r
712 const Can_HardwareObjectType* hoh;
\r
713 hoh = canHwConfig->Can_Arc_Hoh;
\r
719 if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
721 Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;
\r
722 Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;
\r
723 Can_Global.CanHTHMap[hoh->CanObjectId].HxHRef = hoh->CanObjectId;
\r
725 } while (!hoh->Can_Arc_EOL);
\r
730 // Could install handlers depending on HW objects to trap more errors
\r
731 // in configuration
\r
732 switch( canHwConfig->CanControllerId ) {
\r
734 ISR_INSTALL_ISR2( "Can", Can_A_BusOff, FLEXCAN_A_ESR_BOFF_INT, 2, 0);
\r
735 ISR_INSTALL_ISR2( "Can", Can_A_Err, FLEXCAN_A_ESR_ERR_INT, 2, 0 );
\r
736 INSTALL_HANDLER16( "Can", Can_A_Isr, FLEXCAN_A_IFLAG1_BUF0I, 2, 0 );
\r
737 ISR_INSTALL_ISR2( "Can", Can_A_Isr, FLEXCAN_A_IFLAG1_BUF31_16I, 2, 0 );
\r
740 ISR_INSTALL_ISR2( "Can", Can_B_BusOff, FLEXCAN_B_ESR_BOFF_INT, 2, 0 );
\r
741 ISR_INSTALL_ISR2( "Can", Can_B_Err, FLEXCAN_B_ESR_ERR_INT, 2, 0 );
\r
742 INSTALL_HANDLER16( "Can", Can_B_Isr, FLEXCAN_B_IFLAG1_BUF0I, 2, 0 );
\r
743 ISR_INSTALL_ISR2( "Can", Can_B_Isr, FLEXCAN_B_IFLAG1_BUF31_16I, 2, 0 );
\r
746 ISR_INSTALL_ISR2( "Can", Can_C_BusOff, FLEXCAN_C_ESR_BOFF_INT, 2, 0 );
\r
747 ISR_INSTALL_ISR2( "Can", Can_C_Err, FLEXCAN_C_ESR_ERR_INT, 2, 0 );
\r
748 INSTALL_HANDLER16( "Can", Can_C_Isr, FLEXCAN_C_IFLAG1_BUF0I, 2, 0 );
\r
749 ISR_INSTALL_ISR2( "Can", Can_C_Isr, FLEXCAN_C_IFLAG1_BUF31_16I, 2, 0 );
\r
752 ISR_INSTALL_ISR2( "Can", Can_D_BusOff, FLEXCAN_D_ESR_BOFF_INT, 2, 0 );
\r
753 ISR_INSTALL_ISR2( "Can", Can_D_Err, FLEXCAN_D_ESR_ERR_INT, 2, 0 );
\r
754 INSTALL_HANDLER16( "Can", Can_D_Isr, FLEXCAN_D_IFLAG1_BUF0I, 2, 0 );
\r
755 ISR_INSTALL_ISR2( "Can", Can_D_Isr, FLEXCAN_D_IFLAG1_BUF31_16I, 2, 0 );
\r
758 ISR_INSTALL_ISR2( "Can", Can_E_BusOff, FLEXCAN_E_ESR_BOFF_INT, 2, 0 );
\r
759 ISR_INSTALL_ISR2( "Can", Can_E_Err, FLEXCAN_E_ESR_ERR_INT, 2, 0 );
\r
760 INSTALL_HANDLER16( "Can", Can_E_Isr, FLEXCAN_E_IFLAG1_BUF0I, 2, 0 );
\r
761 ISR_INSTALL_ISR2( "Can", Can_E_Isr, FLEXCAN_E_IFLAG1_BUF31_16I, 2, 0 );
\r
763 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
765 ISR_INSTALL_ISR2( "Can", Can_F_BusOff, FLEXCAN_F_ESR_BOFF_INT, 2, 0 );
\r
766 ISR_INSTALL_ISR2( "Can", Can_F_Err, FLEXCAN_F_ESR_ERR_INT, 2, 0 );
\r
767 INSTALL_HANDLER16( "Can", Can_F_Isr, FLEXCAN_F_IFLAG1_BUF0I, 2, 0 );
\r
768 ISR_INSTALL_ISR2( "Can", Can_F_Isr, FLEXCAN_F_IFLAG1_BUF31_16I, 2, 0 );
\r
778 // Unitialize the module
\r
781 Can_UnitType *canUnit;
\r
782 const Can_ControllerConfigType *canHwConfig;
\r
785 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
786 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
787 ctlrId = canHwConfig->CanControllerId;
\r
789 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
790 canUnit->state = CANIF_CS_UNINIT;
\r
792 Can_DisableControllerInterrupts(ctlrId);
\r
794 canUnit->lock_cnt = 0;
\r
797 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
800 Can_Global.config = NULL;
\r
801 Can_Global.initRun = CAN_UNINIT;
\r
806 void Can_InitController( uint8 controller, const Can_ControllerConfigType *config) {
\r
814 Can_UnitType *canUnit;
\r
815 uint8 cId = controller;
\r
816 const Can_ControllerConfigType *canHwConfig;
\r
817 const Can_HardwareObjectType *hohObj;
\r
819 VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );
\r
820 VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);
\r
821 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );
\r
823 canUnit = GET_PRIVATE_DATA(controller);
\r
825 VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );
\r
827 canHw = GET_CONTROLLER(cId);
\r
828 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);
\r
830 // Start this baby up
\r
831 canHw->MCR.B.MDIS = 0;
\r
833 // Wait for it to reset
\r
834 if( !SIMULATOR() ) {
\r
835 // Make a reset so we have a known state
\r
836 canHw->MCR.B.SOFTRST = 1;
\r
837 while( canHw->MCR.B.SOFTRST == 1);
\r
838 // Freeze to write all mem mapped registers ( see 25.4.8.1 )
\r
839 canHw->MCR.B.FRZ = 1;
\r
840 while( canHw->MCR.B.FRZACK == 0);
\r
843 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
845 // FIFO implemenation not tested
\r
846 if( config->Can_Arc_Fifo ) {
\r
847 canHw->MCR.B.FEN = 1; // Enable FIFO
\r
848 canHw->MCR.B.IDAM = 0; // We want extended id's to match with
\r
850 canHw->MCR.B.BCC = 1; // Enable all nice features
\r
852 /* Use Fsys derivate */
\r
853 canHw->CR.B.CLKSRC = 1;
\r
854 canHw->MCR.B.MAXMB = MAX_NUM_OF_MAILBOXES - 1;
\r
856 /* Disable selfreception */
\r
857 canHw->MCR.B.SRXDIS = !config->Can_Arc_Loopback;
\r
859 // Clock calucation
\r
860 // -------------------------------------------------------------------
\r
862 // * 1 TQ = Sclk period( also called SCK )
\r
863 // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk
\r
864 // ( Fcanclk can come from crystal or from the peripheral dividers )
\r
867 // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )
\r
868 // TQ is between 8 and 25
\r
870 // Calculate the number of timequanta's
\r
871 // From "Protocol Timing"( chap. 25.4.7.4 )
\r
872 tq1 = ( config->CanControllerPropSeg + config->CanControllerSeg1 + 2);
\r
873 tq2 = (config->CanControllerSeg2 + 1);
\r
874 tq = 1 + tq1 + tq2;
\r
876 // Check TQ limitations..
\r
877 VALIDATE_DEM_NO_RV(( (tq1>=4) && (tq1<=16)), CAN_E_TIMEOUT );
\r
878 VALIDATE_DEM_NO_RV(( (tq2>=2) && (tq2<=8)), CAN_E_TIMEOUT );
\r
879 VALIDATE_DEM_NO_RV(( (tq>8) && (tq<25 )), CAN_E_TIMEOUT );
\r
881 // Assume we're using the peripheral clock instead of the crystal.
\r
882 clock = McuE_GetPeripheralClock(config->CanCpuClockRef);
\r
884 canHw->CR.B.PRESDIV = clock/(config->CanControllerBaudRate*1000*tq) - 1;
\r
885 canHw->CR.B.PROPSEG = config->CanControllerPropSeg;
\r
886 canHw->CR.B.PSEG1 = config->CanControllerSeg1;
\r
887 canHw->CR.B.PSEG2 = config->CanControllerSeg2;
\r
888 canHw->CR.B.SMP = 1; // 3 samples better than 1 ??
\r
889 canHw->CR.B.LPB = config->Can_Arc_Loopback;
\r
890 canHw->CR.B.BOFFREC = 1; // Disable bus off recovery
\r
892 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
893 // Check if we use individual masks. If so accept anything(=0) for now
\r
894 if( canHw->MCR.B.BCC ) {
\r
895 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
897 canHw->RXIMR[i].R = 0;
\r
901 #if defined(CFG_MPC5567)
\r
902 // Enable individual Rx ID masking and the reception queue features.
\r
903 canHw->MCR.B.MBFEN = 1;
\r
906 if( config->Can_Arc_Fifo ) {
\r
907 // Clear ID's in FIFO also, MUST set extended bit here
\r
908 uint32_t *fifoId = (uint32_t*)(((uint8_t *)canHw)+0xe0);
\r
909 for(int k=0;k<8;k++) {
\r
910 fifoId[k] = 0x40000000; // accept extended frames
\r
914 // Mark all slots as inactive( depending on fifo )
\r
915 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
916 for(; i < 63; i++) {
\r
917 //canHw->BUF[i].CS.B.CODE = 0;
\r
918 canHw->BUF[i].CS.R = 0;
\r
919 canHw->BUF[i].ID.R = 0;
\r
923 /* Build a global interrupt/mb mask for all Hoh's */
\r
926 Can_FilterMaskType mask = 0xffffffff;
\r
929 hohObj = canHwConfig->Can_Arc_Hoh;
\r
934 mbMask = hohObj->Can_Arc_MbMask;
\r
937 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
\r
939 for(;mbMask;mbMask&=~(1<<mbNr)) {
\r
940 mbNr = ilog2(mbMask);
\r
941 canHw->BUF[mbNr].CS.B.CODE = MB_RX;
\r
942 if ( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED )
\r
944 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
945 #if defined(CFG_MPC5567)
\r
946 canHw->RXIMR[mbNr].B.MI = *hohObj->CanFilterMaskRef;
\r
948 canHw->BUF[mbNr].ID.R = *hohObj->CanFilterMaskRef; // Write 29-bit MB IDs
\r
953 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
954 #if defined(CFG_MPC5567)
\r
955 canHw->RXIMR[mbNr].B.MI = *hohObj->CanFilterMaskRef;
\r
957 canHw->BUF[mbNr].ID.B.STD_ID = *hohObj->CanFilterMaskRef;
\r
962 // Add to global mask
\r
963 canUnit->Can_Arc_RxMbMask |= hohObj->Can_Arc_MbMask;
\r
964 if( hohObj->CanFilterMaskRef != NULL ) {
\r
965 mask &= *hohObj->CanFilterMaskRef;
\r
970 canUnit->Can_Arc_TxMbMask |= hohObj->Can_Arc_MbMask;
\r
972 } while( !hohObj->Can_Arc_EOL );
\r
974 #if defined(CFM_MPC5567)
\r
977 canHw->RXGMASK.R = mask;
\r
979 canHw->RX14MASK.R = 0;
\r
980 canHw->RX15MASK.R = 0;
\r
984 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
\r
986 canUnit->state = CANIF_CS_STOPPED;
\r
987 Can_EnableControllerInterrupts(cId);
\r
993 Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {
\r
995 Can_ReturnType rv = CAN_OK;
\r
996 VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );
\r
998 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1000 VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );
\r
1001 canHw = GET_CONTROLLER(controller);
\r
1003 switch(transition )
\r
1006 canHw->MCR.B.FRZ = 0;
\r
1007 canHw->MCR.B.HALT = 0;
\r
1008 canUnit->state = CANIF_CS_STARTED;
\r
1009 imask_t state = McuE_EnterCriticalSection();
\r
1010 if (canUnit->lock_cnt == 0) // REQ CAN196
\r
1012 Can_EnableControllerInterrupts(controller);
\r
1014 McuE_ExitCriticalSection(state);
\r
1016 case CAN_T_WAKEUP: //CAN267
\r
1017 case CAN_T_SLEEP: //CAN258, CAN290
\r
1018 // Should be reported to DEM but DET is the next best
\r
1019 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1022 canHw->MCR.B.FRZ = 1;
\r
1023 canHw->MCR.B.HALT = 1;
\r
1024 canUnit->state = CANIF_CS_STOPPED;
\r
1025 Can_AbortTx( canHw, canUnit ); // CANIF282
\r
1028 // Should be reported to DEM but DET is the next best
\r
1029 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1036 void Can_DisableControllerInterrupts( uint8 controller )
\r
1038 Can_UnitType *canUnit;
\r
1041 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );
\r
1043 canUnit = GET_PRIVATE_DATA(controller);
\r
1045 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );
\r
1047 imask_t state = McuE_EnterCriticalSection();
\r
1048 if(canUnit->lock_cnt > 0 )
\r
1050 // Interrupts already disabled
\r
1051 canUnit->lock_cnt++;
\r
1052 McuE_ExitCriticalSection(state);
\r
1055 canUnit->lock_cnt++;
\r
1056 McuE_ExitCriticalSection(state);
\r
1058 /* Don't try to be intelligent, turn everything off */
\r
1059 canHw = GET_CONTROLLER(controller);
\r
1061 /* Turn off the interrupt mailboxes */
\r
1062 canHw->IMRH.R = 0;
\r
1063 canHw->IMRL.R = 0;
\r
1065 /* Turn off the bus off/tx warning/rx warning and error */
\r
1066 canHw->MCR.B.WRNEN = 0; /* Disable warning int */
\r
1067 canHw->CR.B.ERRMSK = 0; /* Disable error interrupt */
\r
1068 canHw->CR.B.BOFFMSK = 0; /* Disable bus-off interrupt */
\r
1069 canHw->CR.B.TWRNMSK = 0; /* Disable Tx warning */
\r
1070 canHw->CR.B.RWRNMSK = 0; /* Disable Rx warning */
\r
1073 void Can_EnableControllerInterrupts( uint8 controller ) {
\r
1074 Can_UnitType *canUnit;
\r
1076 const Can_ControllerConfigType *canHwConfig;
\r
1077 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );
\r
1079 canUnit = GET_PRIVATE_DATA(controller);
\r
1081 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );
\r
1083 imask_t state = McuE_EnterCriticalSection();
\r
1084 if( canUnit->lock_cnt > 1 )
\r
1086 // IRQ should still be disabled so just decrement counter
\r
1087 canUnit->lock_cnt--;
\r
1088 McuE_ExitCriticalSection(state);
\r
1090 } else if (canUnit->lock_cnt == 1)
\r
1092 canUnit->lock_cnt = 0;
\r
1094 McuE_ExitCriticalSection(state);
\r
1096 canHw = GET_CONTROLLER(controller);
\r
1098 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);
\r
1100 canHw->IMRH.R = 0;
\r
1101 canHw->IMRL.R = 0;
\r
1103 if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1104 /* Turn on the interrupt mailboxes */
\r
1105 canHw->IMRL.R = canUnit->Can_Arc_RxMbMask;
\r
1108 if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1109 /* Turn on the interrupt mailboxes */
\r
1110 canHw->IMRL.R |= canUnit->Can_Arc_TxMbMask;
\r
1113 // BusOff here represents all errors and warnings
\r
1114 if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1115 canHw->MCR.B.WRNEN = 1; /* Turn On warning int */
\r
1117 canHw->CR.B.ERRMSK = 1; /* Enable error interrupt */
\r
1118 canHw->CR.B.BOFFMSK = 1; /* Enable bus-off interrupt */
\r
1119 canHw->CR.B.TWRNMSK = 1; /* Enable Tx warning */
\r
1120 canHw->CR.B.RWRNMSK = 1; /* Enable Rx warning */
\r
1126 Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {
\r
1129 Can_ReturnType rv = CAN_OK;
\r
1132 const Can_HardwareObjectType *hohObj;
\r
1133 uint32 controller;
\r
1136 VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );
\r
1137 VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );
\r
1138 VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );
\r
1139 VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );
\r
1141 hohObj = Can_FindHoh(hth, &controller);
\r
1142 if (hohObj == NULL)
\r
1143 return CAN_NOT_OK;
\r
1145 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1147 canHw = GET_CONTROLLER(controller);
\r
1148 oldMsr = McuE_EnterCriticalSection();
\r
1149 iflag = canHw->IFRL.R & canUnit->Can_Arc_TxMbMask;
\r
1151 // check for any free box
\r
1152 // Normally we would just use the iflag to get the free box
\r
1153 // but that does not work the first time( iflag == 0 ) so we
\r
1154 // create one( iflagStart )
\r
1155 if( iflag | canUnit->iflagStart ) {
\r
1156 mbNr = ilog2((iflag | canUnit->iflagStart)); // find mb number
\r
1158 canHw->IFRL.R = (1<<mbNr);
\r
1159 canUnit->iflagStart &= ~(1<<mbNr);
\r
1161 // Setup message box type
\r
1162 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1163 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
1164 } else if ( hohObj->CanIdType == CAN_ID_TYPE_STANDARD ) {
\r
1165 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
1167 // No support for mixed in this processor
\r
1172 canHw->BUF[mbNr].CS.B.CODE = MB_INACTIVE; // Hold the transmit buffer inactive
\r
1173 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1174 canHw->BUF[mbNr].ID.R = pduInfo->id; // Write 29-bit MB IDs
\r
1176 assert( !(pduInfo->id & 0xfffff800) );
\r
1177 canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;
\r
1180 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
1181 canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority
\r
1184 memset(&canHw->BUF[mbNr].DATA, 0, 8);
\r
1185 memcpy(&canHw->BUF[mbNr].DATA, pduInfo->sdu, pduInfo->length);
\r
1187 canHw->BUF[mbNr].CS.B.SRR = 1;
\r
1188 canHw->BUF[mbNr].CS.B.RTR = 0;
\r
1190 canHw->BUF[mbNr].CS.B.LENGTH = pduInfo->length;
\r
1191 canHw->BUF[mbNr].CS.B.CODE = MB_TX_ONCE; // Write tx once code
\r
1192 timer = canHw->TIMER.R; // Unlock Message buffers
\r
1194 canUnit->stats.txSuccessCnt++;
\r
1196 // Store pdu handle in unit to be used by TxConfirmation
\r
1197 canUnit->swPduHandles[mbNr] = pduInfo->swPduHandle;
\r
1202 McuE_ExitCriticalSection(oldMsr);
\r
1207 void Can_MainFunction_Read( void ) {
\r
1209 /* NOT SUPPORTED */
\r
1212 void Can_MainFunction_BusOff( void ) {
\r
1213 /* Bus-off polling events */
\r
1215 /* NOT SUPPORTED */
\r
1218 void Can_MainFunction_Wakeup( void ) {
\r
1219 /* Wakeup polling events */
\r
1221 /* NOT SUPPORTED */
\r
1226 * Get send/receive/error statistics for a controller
\r
1228 * @param controller The controller
\r
1229 * @param stats Pointer to data to copy statistics to
\r
1232 void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)
\r
1234 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1235 *stats = canUnit->stats;
\r
1240 #else // Stub all functions for use in simulator environment
\r
1242 #include "debug.h"
\r
1244 void Can_Init( const Can_ConfigType *Config )
\r
1246 // Do initial configuration of layer here
\r
1249 void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)
\r
1251 // Do initialisation of controller here.
\r
1254 Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )
\r
1256 // Turn on off controller here depending on transition
\r
1260 Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )
\r
1262 // Write to mailbox on controller here.
\r
1263 DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");
\r
1264 for (int i = 0; i < pduInfo->length; i++) {
\r
1265 DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);
\r
1267 DEBUG(DEBUG_MEDIUM, "\n");
\r
1272 extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);
\r
1273 Can_ReturnType Can_ReceiveAFrame()
\r
1275 // This function is not part of autosar but needed to feed the stack with data
\r
1276 // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.
\r
1277 uint8 CanSduData[] = {1,2,1,0,0,0,0,0};
\r
1278 CanIf_RxIndication(CAN_HRH_A_1, 3, 8, CanSduData);
\r
1283 void Can_DisableControllerInterrupts( uint8 controller )
\r
1287 void Can_EnableControllerInterrupts( uint8 controller )
\r
1292 // Hth - for Flexcan, the hardware message box number... .We don't care
\r
1293 void Can_Cbk_CheckWakeup( uint8 controller ){}
\r
1295 void Can_MainFunction_Write( void ){}
\r
1296 void Can_MainFunction_Read( void ){}
\r
1297 void Can_MainFunction_BusOff( void ){}
\r
1298 void Can_MainFunction_Wakeup( void ){}
\r
1300 void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}
\r